arch/powerpc/platforms/44x/cpm.c

103

dcr_write(cpm.dcr_host, cpm.dcr_offset[CPM_ER], er_save);

arch/powerpc/platforms/44x/cpm.c

70

dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask);

arch/powerpc/platforms/44x/pci.c

1018

dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);

arch/powerpc/platforms/44x/pci.c

1356

dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,

arch/powerpc/platforms/44x/pci.c

1358

dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,

arch/powerpc/platforms/44x/pci.c

1362

dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);

arch/powerpc/platforms/44x/pci.c

1365

dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,

arch/powerpc/platforms/44x/pci.c

1367

dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,

arch/powerpc/platforms/44x/pci.c

1371

dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);

arch/powerpc/platforms/44x/pci.c

1374

dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);

arch/powerpc/platforms/44x/pci.c

1375

dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);

arch/powerpc/platforms/44x/pci.c

1376

dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);

arch/powerpc/platforms/44x/pci.c

1377

dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);

arch/powerpc/platforms/44x/pci.c

1515

dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);

arch/powerpc/platforms/44x/pci.c

1545

dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);

arch/powerpc/platforms/44x/pci.c

1570

dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);

arch/powerpc/platforms/44x/pci.c

1589

dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);

arch/powerpc/platforms/44x/pci.c

1631

dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);

arch/powerpc/platforms/44x/pci.c

1632

dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);

arch/powerpc/platforms/44x/pci.c

1633

dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);

arch/powerpc/platforms/44x/pci.c

1636

dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,

arch/powerpc/platforms/44x/pci.c

1643

dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,

arch/powerpc/platforms/44x/pci.c

1647

dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,

arch/powerpc/platforms/44x/pci.c

1654

dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);

arch/powerpc/platforms/44x/pci.c

1655

dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);

arch/powerpc/platforms/44x/pci.c

1656

dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);

arch/powerpc/platforms/44x/pci.c

1657

dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,

arch/powerpc/platforms/44x/pci.c

1663

dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);

arch/powerpc/platforms/44x/pci.c

1664

dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);

arch/powerpc/platforms/44x/pci.c

1665

dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);

arch/powerpc/platforms/44x/pci.c

1667

dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,

arch/powerpc/platforms/44x/pci.c

891

dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);

arch/powerpc/sysdev/mpic.c

200

dcr_write(rb->dhost, reg, value);

drivers/dma/ppc4xx/adma.c

4330

dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_XORBA, val);

drivers/dma/ppc4xx/adma.c

4391

dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL, reg);

drivers/dma/ppc4xx/adma.c

4471

dcr_write(i2o_dcr_host, DCRN_I2O0_IBAH, (u32)(i2o_res.start >> 32));

drivers/dma/ppc4xx/adma.c

4472

dcr_write(i2o_dcr_host, DCRN_I2O0_IBAL, (u32)(i2o_res.start) |

drivers/dma/ppc4xx/adma.c

4518

dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_BAUH, DMA_CUED_XOR_HB);

drivers/dma/ppc4xx/adma.c

4525

dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL,

drivers/dma/ppc4xx/adma.c

671

dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CF2H, byte_count);

drivers/net/ethernet/ibm/emac/mal.h

220

dcr_write(mal->dcr_host, reg, val);

drivers/net/ethernet/xilinx/ll_temac_main.c

254

dcr_write(lp->sdma_dcrs, reg, value);

drivers/video/fbdev/xilinxfb.c

177

dcr_write(drvdata->dcr_host, offset, val);