dcn32_smu_set_hard_min_by_freq
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);