cx_set
cx_set(MC417_RWD, NETUP_CTRL_OFF);
cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
cx_set(DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */
cx_set(AUD_INT_DMA_CTL, 0x11); /* audio downstream FIFO and
cx_set(GP0_IO, 0x00070007);
cx_set(GP0_IO,
cx_set(GP0_IO, 7);
cx_set(GP0_IO, bitmask);
cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
cx_set(GP0_IO, 0x00050000);
cx_set(GP0_IO, 0x00050005);
cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
cx_set(GP0_IO, 0x00050000);
cx_set(GP0_IO, 0x00050005);
cx_set(GP0_IO, 0x00050000);
cx_set(GP0_IO, 0x00050005);
cx_set(GP0_IO, 0x00050000);
cx_set(GP0_IO, 0x00050005);
cx_set(GP0_IO, 0x000f0000);
cx_set(GP0_IO, 0x000f000f);
cx_set(GP0_IO, 0x000f0000);
cx_set(GP0_IO, 0x000f000f);
cx_set(GP0_IO, 0x00040000);
cx_set(GP0_IO, 0x00040004);
cx_set(MC417_RWD, 0x00000002);
cx_set(MC417_RWD, 0x00000800);
cx_set(GP0_IO, 0x00040000); /* GPIO as out */
cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
cx_set(GP0_IO, 0x00000004); /* reset high */
cx_set(GP0_IO, 0x00070000);
cx_set(GP0_IO, 0x00010001);
cx_set(GP0_IO, 0x00010001);
cx_set(GP0_IO, 0x00020002);
cx_set(GP0_IO, 0x00010001);
cx_set(GP0_IO, 0x00040004);
cx_set(GP0_IO, 0x00040004);
cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
cx_set(port->reg_dma_ctl, port->dma_ctl_val);
cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
cx_set(GP0_IO, mask & 0x7);
cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
cx_set(GP0_IO, (mask & 0x7) << 16);
cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
cx_set(PCI_INT_MSK, mask);
cx_set(PCI_INT_MSK, v);
cx_set(MC417_RWD, SP2_CTRL_OFF);
cx_set(MC417_OEN, ALT_DATA);
cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
cx_set(VID_A_INT_MSK, 0x000022);
cx_set(DEV_CNTRL2, (1<<5));
cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
cx_set(VID_A_INT_MSK, 0x000011);
cx_set(DEV_CNTRL2, (1<<5));
cx_set(VID_A_DMA_CTL, 0x11); /* FIFO and RISC enable */
cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
cx_set(AUD_INT_DMA_CTL, tmp |
cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i));
cx_set(channel->int_msk, 0x11);
cx_set(PCI_INT_MSK, 0xff);
cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT);
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_AUD_DMACNTRL, 0x11);
cx_set(MO_GP0_IO, 0x00000080);
cx_set(MO_GP0_IO, 0x00000080);
cx_set(MO_GP0_IO, 0x00000004);
cx_set(MO_GP0_IO, 0x008989FF);
cx_set(MO_GP0_IO, 0x00001000);
cx_set(MO_GP0_IO, 0x00000010);
cx_set(MO_GP0_IO, 0x101010);
cx_set(MO_GP1_IO, 0x1010);
cx_set(MO_GP1_IO, 0x10);
cx_set(MO_GP1_IO, 0x1010);
cx_set(MO_GP1_IO, 0x10);
cx_set(MO_GP0_IO, 0x00000010);
cx_set(MO_GP0_IO, 0x00000088); /* 702 out of reset */
cx_set(MO_GP0_IO, 0x00001010);
cx_set(MO_GP0_IO, 0x00000080); /* 702 out of reset */
cx_set(MO_GP0_IO, 0x00004040);
cx_set(MO_GP0_IO, 0x00004040);
cx_set(MO_GP0_IO, 0x00000101);
cx_set(MO_GP0_IO, 0x00000101);
cx_set(MO_GP0_IO, 0x00000707);
cx_set(MO_GP2_IO, 0x00000101);
cx_set(MO_GP2_IO, 0x00000101);
cx_set(MO_GP0_IO, 1);
cx_set(MO_GP0_IO, 9);
cx_set(MO_GP0_IO, 1);
cx_set(MO_GP0_IO, 1);
cx_set(MO_GP0_IO, 0x0101);
cx_set(MO_GP0_IO, 0x01);
cx_set(MO_GP0_IO, 0x00000080);
cx_set(MO_GP0_IO, 0x00000080);
cx_set(MO_GP0_IO, 0x00000080);
cx_set(MO_GP0_IO, 0x00000080);
cx_set(MO_GP0_IO, 0x00000004);
cx_set(MO_GP0_IO, 8);
cx_set(MO_GP0_IO, 0x6040);
cx_set(MO_GP0_IO, 0x20);
cx_set(MO_GP0_IO, 0x0800);
cx_set(MO_GP0_IO, 0x08);
cx_set(MO_GP0_IO, 0x8000);
cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_TSINT);
cx_set(MO_TS_INTMSK, 0x1f0011);
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_TS_DMACNTRL, 0x11);
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
cx_set(AUD_CTL, EN_I2SOUT_ENABLE);
cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
cx_set(MO_VID_INTMSK, 0x0f0088);
cx_set(VID_CAPTURE_CONTROL, 0x18);
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_VID_DMACNTRL, 0x88);
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
cx_set(MO_AFECFG_IO, 0x00000001);
cx_set(MO_INPUT_FORMAT, 0x00010010);
cx_set(MO_FILTER_EVEN, 0x00002020);
cx_set(MO_FILTER_ODD, 0x00002020);
cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
cx_set(MO_VID_INTMSK, 0x0f0011);
cx_set(VID_CAPTURE_CONTROL, 0x06);
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */