drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2089

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2620

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2838

struct dce_hwseq *hws = params->dsc_pg_status_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2887

struct dce_hwseq *hws = params->dpp_pg_control_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2897

struct dce_hwseq *hws = params->hubp_pg_control_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2923

struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2935

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3025

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3618

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3670

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3684

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3698

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

741

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

948

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/dc.h

1782

struct dce_hwseq *hwseq;

drivers/gpu/drm/amd/display/dc/dc.h

974

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

138

static void dce_disable_sram_shut_down(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

145

static void dce_underlay_clock_enable(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

163

void dce_clock_gating_power_up(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

175

void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

40

void dce_enable_fe_clock(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

53

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

97

void dce_set_blender_mode(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1275

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1279

void dce_enable_fe_clock(struct dce_hwseq *hwss,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1286

void dce_set_blender_mode(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1295

void dce_clock_gating_power_up(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1298

void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1194

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1212

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1578

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1903

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2449

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2809

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2918

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3068

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

195

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

251

bool dce121_xgmi_enabled(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h

34

bool dce121_xgmi_enabled(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

278

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1009

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1036

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1056

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1086

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1445

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1492

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1523

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1556

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1573

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1765

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1952

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2153

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

256

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2650

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2675

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2717

static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2735

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2982

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3209

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3338

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3376

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3563

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3625

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3638

void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4029

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

832

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

854

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

896

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

957

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

102

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

106

struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

121

void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

94

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

98

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1104

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1266

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1669

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1895

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1920

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2039

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2239

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2477

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2601

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2616

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2650

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2671

int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2751

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2894

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

309

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3122

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

358

void dcn20_dccg_init(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

367

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

394

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

460

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

537

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

619

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

697

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

821

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

100

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

103

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

107

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

126

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

134

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

140

void dcn20_dccg_init(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

141

int dcn20_init_sys_ctx(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

97

struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

110

static void plane_address_in_gpu_space_to_uma(struct dce_hwseq *hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

141

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

171

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

205

static void read_mmhub_vm_setup(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

230

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

382

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

533

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

600

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

88

static bool gpu_addr_to_uma(struct dce_hwseq *hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

54

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

68

int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

33

int dcn21_init_sys_ctx(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

320

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

644

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

102

void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

159

void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

45

void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h

31

void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h

32

void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h

33

void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

46

void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

51

void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

56

void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

61

void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

32

void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

33

void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

34

void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

35

void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

114

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

280

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

344

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

446

void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

485

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

616

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

658

void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

74

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

36

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

41

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

49

void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

50

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

59

void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

226

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

296

void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

369

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

399

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

456

void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

544

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

36

void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

38

void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

44

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

46

void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

50

void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1196

struct dce_hwseq *hws = stream->ctx->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1234

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1251

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1316

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

138

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1490

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1525

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1546

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1581

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1643

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

167

void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

533

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

71

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

731

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

788

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

107

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

34

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

39

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

42

void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

78

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

126

void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

135

void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

143

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

481

void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

492

void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

503

void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

624

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

80

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

896

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

36

void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

38

void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

40

void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

42

void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

44

void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

46

void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

85

void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

87

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1013

void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

143

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1765

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2056

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2114

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2139

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2265

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2408

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2573

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2705

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2954

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3047

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3519

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3529

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3590

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

770

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

57

void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1022

void (*update_dchub)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1118

int (*init_sys_ctx)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1121

void (*init_vm_ctx)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1263

void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1849

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1867

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1872

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1877

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

47

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

578

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

584

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

598

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

609

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

123

void (*disable_vga)(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

133

void (*enable_power_gating_plane)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

136

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

140

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

144

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

147

void (*dpp_pg_control)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

150

void (*hubp_pg_control)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

153

void (*dsc_pg_control)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

156

bool (*dsc_pg_status)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

186

void (*dccg_init)(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

195

void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

206

void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

69

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/inc/resource.h

93

struct dce_hwseq *(*create_hwseq)(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

520

static struct dce_hwseq *dce100_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

523

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1135

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

563

static struct dce_hwseq *dce110_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

566

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

540

static struct dce_hwseq *dce112_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

543

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

813

static struct dce_hwseq *dce120_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

816

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

827

static struct dce_hwseq *dce121_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

830

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

638

static struct dce_hwseq *dce60_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

641

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

644

static struct dce_hwseq *dce80_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

647

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

873

static struct dce_hwseq *dcn10_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

876

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1059

struct dce_hwseq *dcn20_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1062

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1260

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

73

struct dce_hwseq *dcn20_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

912

static struct dce_hwseq *dcn201_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

915

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1193

static struct dce_hwseq *dcn21_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1196

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1075

static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1077

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1046

static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1048

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

503

static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

505

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

487

static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

489

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1351

static struct dce_hwseq *dcn31_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1354

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1410

static struct dce_hwseq *dcn314_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1413

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1352

static struct dce_hwseq *dcn31_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1355

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1347

static struct dce_hwseq *dcn31_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1350

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1355

static struct dce_hwseq *dcn32_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1358

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1336

static struct dce_hwseq *dcn321_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1339

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1419

static struct dce_hwseq *dcn35_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1422

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1399

static struct dce_hwseq *dcn351_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1402

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1406

static struct dce_hwseq *dcn36_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1409

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1354

static struct dce_hwseq *dcn401_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1357

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);