drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

147

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

232

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

237

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

259

dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

263

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

267

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

271

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

274

dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

285

vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

298

dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

310

dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

322

dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

333

dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

345

dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

358

dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

360

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

367

struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

48

int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

109

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

119

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

122

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

123

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

155

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

168

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

169

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

172

dccg->funcs->otg_drop_pixel(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

173

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

175

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

176

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

185

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

199

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

201

dccg->funcs->otg_add_pixel(dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

203

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

396

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

532

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

546

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

29

void dcn2_update_clocks(struct clk_mgr *dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

44

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

182

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

192

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h

32

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

111

clk_mgr->dccg->ref_dppclk = ref_dpp_clk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

122

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

125

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

126

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

704

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

719

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

47

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

524

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

534

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

94

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

681

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

691

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

48

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

677

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

687

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

52

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

794

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

804

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

64

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

607

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

617

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

45

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

582

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

592

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

45

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1148

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1164

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

270

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

286

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

319

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

340

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

343

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

344

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

374

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

387

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

388

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

391

dccg->funcs->otg_drop_pixel(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

392

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

394

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

395

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

427

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

441

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

443

dccg->funcs->otg_add_pixel(dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

445

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

33

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

130

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

137

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1286

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1401

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1410

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

202

struct dccg *dccg = clk_mgr_internal->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

233

has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

234

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

240

!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

258

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

274

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

287

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

308

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

311

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

312

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

320

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

59

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

66

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1549

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1565

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

529

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

542

use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

550

dccg->ctx->dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

561

clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

582

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

585

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

586

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

111

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/core/dc.c

1162

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/core/dc.c

6805

state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

6812

state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

6813

state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/core/dc.c

6814

state->dccg.dppclk_enable[i] = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

6819

state->dccg.dpstreamclk_enable[i] = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

6821

state->dccg.dpstreamclk_enable[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6825

state->dccg.dppclk_khz[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6826

state->dccg.pixclk_khz[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6827

state->dccg.dppclk_enable[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6829

state->dccg.dpstreamclk_enable[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6838

state->dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */

drivers/gpu/drm/amd/display/dc/core/dc.c

6840

state->dccg.dscclk_khz[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6846

state->dccg.symclk32_le_enable[i] = 0; /* Default: disabled */

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2252

struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2256

if (dccg && dccg->funcs->set_dto_dscclk)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2257

dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2873

struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2881

if (dccg && dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2882

dccg->funcs->set_ref_dscclk(dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2943

struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2947

if (dccg && dccg->funcs->update_dpp_dto)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2948

dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3150

struct dccg *dccg, int inst, int num_slices_h)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3154

seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3656

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3662

seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3780

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3786

seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/dc.h

3074

} dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

102

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

108

void dccg2_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

111

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

120

void dccg2_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

123

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

132

void dccg2_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

134

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

148

void dccg2_refclk_setup(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

150

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

157

bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

159

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

164

void dccg2_allow_clock_gating(struct dccg *dccg, bool allow)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

166

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

177

void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

179

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

197

struct dccg *dccg2_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

204

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

222

void dcn_dccg_destroy(struct dccg **dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

224

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

227

*dccg = NULL;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

32

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

45

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

47

void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

51

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

52

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

74

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

77

void dccg2_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

81

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

99

void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

503

struct dccg base;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

509

void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

511

void dccg2_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

515

void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

517

void dccg2_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

519

void dccg2_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

523

void dccg2_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

525

void dccg2_refclk_setup(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

526

void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

527

void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

528

bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

530

struct dccg *dccg2_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

536

void dcn_dccg_destroy(struct dccg **dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

32

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

46

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

48

static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

67

struct dccg *dccg201_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

74

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h

31

struct dccg *dccg201_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

111

static void dccg21_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

113

if (dccg2_is_s0i3_golden_init_wa_done(dccg))

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

116

dccg2_init(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

132

struct dccg *dccg21_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

139

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

31

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

44

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

46

static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

48

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

50

if (dccg->ref_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

51

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

96

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h

29

struct dccg *dccg21_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

30

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

43

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

59

struct dccg *dccg3_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

66

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

84

struct dccg *dccg30_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

91

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

54

struct dccg *dccg3_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

60

struct dccg *dccg30_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

30

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

43

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

58

struct dccg *dccg301_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

65

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h

59

struct dccg *dccg301_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

100

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

124

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

130

static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

132

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

134

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

163

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

169

dccg31_disable_dpstreamclk(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

171

dccg31_enable_dpstreamclk(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

175

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

179

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

186

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

195

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

204

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

213

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

228

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

231

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

239

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

248

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

257

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

266

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

278

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

282

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

305

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

308

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

32

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

329

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

333

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

335

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

355

void dccg31_disable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

357

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

359

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

399

void dccg31_enable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

401

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

403

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

444

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

449

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

45

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

458

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

465

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

47

void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

475

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

482

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

492

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

499

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

509

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

51

if (dccg->dpp_clock_gated[dpp_inst]) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

516

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

526

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

533

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

546

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

549

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

59

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

60

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

612

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

615

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

643

void dccg31_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

656

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

659

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

665

void dccg31_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

671

dccg31_disable_symclk32_se(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

672

dccg31_disable_symclk32_se(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

673

dccg31_disable_symclk32_se(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

674

dccg31_disable_symclk32_se(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

676

dccg31_set_symclk32_le_root_clock_gating(dccg, 0, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

677

dccg31_set_symclk32_le_root_clock_gating(dccg, 1, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

679

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

680

dccg31_disable_dpstreamclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

681

dccg31_disable_dpstreamclk(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

682

dccg31_disable_dpstreamclk(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

683

dccg31_disable_dpstreamclk(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

686

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

687

dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

688

dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

689

dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

690

dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

691

dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

695

void dccg31_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

698

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

704

void dccg31_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

707

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

713

void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

715

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

81

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

860

struct dccg *dccg31_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

867

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

98

static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

165

struct dccg *dccg31_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

171

void dccg31_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

174

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

179

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

183

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

188

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

192

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

197

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

203

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

207

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

212

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

217

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

223

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

227

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

231

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

235

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

238

void dccg31_disable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

240

void dccg31_enable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

242

void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

102

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

107

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

118

dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

150

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

154

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

207

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

210

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

232

dccg314_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

251

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

256

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

259

dccg314_set_dtbclk_p_src(dccg, src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

289

static void dccg314_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

298

dccg31_disable_symclk32_se(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

300

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

302

dccg31_disable_symclk32_le(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

304

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

306

dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

309

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

311

dccg31_set_physymclk(dccg, otg_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

316

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

327

dccg314_set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

331

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

335

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

337

if (dccg->dpp_clock_gated[dpp_inst] != clock_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

34

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

35

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

354

dccg->dpp_clock_gated[dpp_inst] = !clock_on;

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

389

struct dccg *dccg314_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

396

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

47

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

50

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

52

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

60

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

65

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

202

struct dccg *dccg314_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

209

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

102

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

107

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

118

dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

150

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

154

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

206

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

209

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

231

dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

249

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

261

dccg32_set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

264

static void dccg32_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

277

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

282

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

286

dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

31

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

313

static void dccg32_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

316

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

322

static void dccg32_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

325

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

357

struct dccg *dccg32_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

364

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

44

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

47

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

60

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

65

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

119

struct dccg *dccg32_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1002

if (dccg35_is_symclk32_se_rcg(dccg, i) == 0) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1004

if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1005

dccg35_disable_symclk32_se_new(dccg, i);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1009

dccg35_set_symclk32_le_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1012

static void dccg35_enable_physymclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1016

dccg35_set_physymclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1017

dccg35_set_physymclk_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1020

static void dccg35_disable_physymclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1023

dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1024

dccg35_set_physymclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1028

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1032

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1038

dccg35_set_dppclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1039

dcn35_set_dppclk_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1048

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1051

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1057

dcn35_set_dppclk_src_new(dccg, inst, DPP_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1061

dccg35_set_dppclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1064

static void dccg35_disable_dscclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1067

dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1068

dccg35_set_dsc_clk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1071

static void dccg35_enable_dscclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1075

dccg35_set_dsc_clk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1076

dccg35_set_dsc_clk_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1079

static void dccg35_enable_dtbclk_p_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1083

dccg35_set_dtbclk_p_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1084

dccg35_set_dtbclk_p_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1087

static void dccg35_disable_dtbclk_p_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1090

dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1091

dccg35_set_dtbclk_p_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1094

static void dccg35_disable_dpstreamclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1097

dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1098

dccg35_set_dpstreamclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1101

static void dccg35_enable_dpstreamclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1105

dccg35_set_dpstreamclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1106

dccg35_set_dpstreamclk_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1109

void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1111

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1120

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1122

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1130

static void dcn35_set_dppclk_enable(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1133

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1156

void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1158

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1160

if (dccg->dpp_clock_gated[dpp_inst]) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1167

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1168

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1179

dccg35_set_dppclk_rcg(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1185

dcn35_set_dppclk_enable(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1187

dcn35_set_dppclk_enable(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1188

dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1191

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1194

static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1197

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1199

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1226

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1231

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1268

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1273

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1285

dccg35_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1315

dccg35_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1319

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1323

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1375

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1378

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

138

static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

140

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1415

dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

142

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1458

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1463

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1466

dccg35_set_dtbclk_p_src(dccg, src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1473

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1479

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1485

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1491

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1502

void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1504

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1508

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1514

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1520

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1526

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1542

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1546

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1548

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1581

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1586

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1654

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1666

dccg35_set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1669

void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1671

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1673

if (dccg->dpp_clock_gated[dpp_inst] != clock_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1677

dccg35_set_dppclk_rcg(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1680

dcn35_set_dppclk_enable(dccg, dpp_inst, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1685

dcn35_set_dppclk_enable(dccg, dpp_inst, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

169

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1691

dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1697

dccg->dpp_clock_gated[dpp_inst] = !clock_on;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1701

void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1703

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1711

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1722

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

173

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1733

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1744

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

175

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1758

static void dccg35_init_cb(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1760

(void)dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1763

void dccg35_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1771

dccg35_disable_symclk32_se(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1773

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1775

dccg31_disable_symclk32_le(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1776

dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1786

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1788

dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1790

dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1801

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1803

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1808

void dccg35_enable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1810

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1855

void dccg35_disable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1857

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1865

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1873

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1881

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1889

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1900

void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1902

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1908

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1914

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1920

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1926

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1932

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1942

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1949

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1956

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1963

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1970

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1977

static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1981

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2007

void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2010

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2051

num_enabled_symclk_fe = dccg35_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

208

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2091

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

212

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2120

dccg35_disable_dtbclk_p_new(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2121

dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2123

dccg35_enable_dtbclk_p_new(dccg, dtb_clk_src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2124

dccg35_enable_dpstreamclk_new(dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2131

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

214

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2142

dccg35_enable_dpstreamclk_new(dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2146

dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2149

static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2152

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2154

if (dccg->dpp_clock_gated[dpp_inst]) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2161

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2162

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2175

dccg35_enable_dpp_clk_new(dccg, dpp_inst, DPP_DCCG_DTO);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2182

dccg35_disable_dpp_clk_new(dccg, dpp_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2184

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2188

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2192

if (dccg->dpp_clock_gated[dpp_inst] == power_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2199

dccg35_set_dppclk_rcg(dccg, dpp_inst, !power_on);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2201

dccg->dpp_clock_gated[dpp_inst] = !power_on;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2205

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2209

dccg35_enable_symclk32_se_new(dccg, inst, (enum symclk32_se_clk_source)phyd32clk);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2212

static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2214

dccg35_disable_symclk32_se_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2218

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2222

dccg35_enable_symclk32_le_new(dccg, inst, (enum symclk32_le_clk_source) src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2225

static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2227

dccg35_disable_symclk32_le_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2231

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2241

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2243

dccg35_disable_symclk32_le_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2247

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2254

dccg35_enable_physymclk_new(dccg, inst, (enum physymclk_source)clk_src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2256

dccg35_disable_physymclk_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2260

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2268

dccg35_enable_physymclk_new(dccg, inst, PHYSYMCLK_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2270

dccg35_disable_physymclk_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2274

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2284

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2286

dccg35_disable_symclk32_le_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2290

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2295

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2297

dccg35_disable_dtbclk_p_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2301

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2307

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2314

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, params->otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2331

dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2340

dccg35_disable_dtbclk_p_new(dccg, params->otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

235

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2351

static void dccg35_disable_dscclk_cb(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2354

dccg35_disable_dscclk_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2357

static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2359

dccg35_enable_dscclk_new(dccg, inst, DSC_DTO_TUNED_CK_GPU_DISCLK_3);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2362

static void dccg35_enable_symclk_se_cb(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2365

dccg35_enable_symclk_be_new(dccg, SYMCLK_BE_PHYCLK, link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2367

dccg35_enable_symclk_fe_new(dccg, stream_enc_inst, (enum symclk_fe_source) link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2372

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2376

dccg35_disable_symclk_fe_new(dccg, stream_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2381

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2383

dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

239

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

241

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2458

struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2465

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

272

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

276

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

278

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

31

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

319

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

324

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

327

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

367

static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

370

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

372

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

394

static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

396

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

398

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

425

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

429

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

431

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

45

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

462

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

466

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

468

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

498

static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

500

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

524

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

529

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

559

dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

564

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

576

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

580

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

599

static void dcn35_set_dppclk_src_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

602

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

624

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

628

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

662

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

666

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

702

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

706

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

746

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

750

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

781

static int dccg35_is_symclk_fe_src_functional_be(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

789

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

815

static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

817

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

848

static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

851

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

881

static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

885

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

918

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

922

dccg35_set_symclk_fe_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

923

dccg35_set_symclk_fe_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

927

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

930

dccg35_set_symclk_fe_src_new(dccg, SYMCLK_FE_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

931

dccg35_set_symclk_fe_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

935

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

939

dccg35_set_symclk_be_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

940

dccg35_set_symclk_be_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

944

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

950

dccg35_set_symclk_be_src_new(dccg, inst, SYMCLK_BE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

955

if (dccg35_is_fe_rcg(dccg, i) == 0) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

956

if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

957

dccg35_disable_symclk_fe_new(dccg, i);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

961

dccg35_set_symclk_be_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

965

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

969

dccg35_set_symclk32_se_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

970

dccg35_set_symclk32_se_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

974

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

977

dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

978

dccg35_set_symclk32_se_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

982

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

986

dccg35_set_symclk32_le_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

987

dccg35_set_symclk32_le_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

991

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

997

dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

244

struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

250

void dccg35_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

252

void dccg35_trigger_dio_fifo_resync(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

254

void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

256

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

257

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

259

void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

261

void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

263

void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

265

void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

267

void dccg35_enable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

268

void dccg35_disable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

270

void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

271

void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

100

dcn401_set_dppclk_enable(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

103

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

110

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

112

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

121

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

126

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

159

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

164

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

174

dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

186

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

192

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

198

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

204

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

214

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

218

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

269

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

274

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

283

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

290

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

300

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

307

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

317

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

324

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

334

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

341

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

352

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

364

static void dccg401_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

367

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

373

static void dccg401_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

376

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

383

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

387

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

392

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

401

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

41

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

410

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

419

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

42

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

434

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

437

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

445

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

454

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

463

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

472

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

483

static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

485

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

490

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

499

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

508

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

517

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

529

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

535

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

537

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

54

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

543

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

551

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

559

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

56

static void dcn401_set_dppclk_enable(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

567

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

579

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

586

dccg401_disable_dpstreamclk(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

588

dccg401_enable_dpstreamclk(dccg, otg_inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

59

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

592

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

595

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

659

dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

693

void dccg401_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

699

dccg31_disable_symclk32_se(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

700

dccg31_disable_symclk32_se(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

701

dccg31_disable_symclk32_se(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

702

dccg31_disable_symclk32_se(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

704

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

705

dccg401_disable_symclk32_le(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

706

dccg401_disable_symclk32_le(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

707

dccg401_disable_symclk32_le(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

708

dccg401_disable_symclk32_le(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

711

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

712

dccg401_disable_dpstreamclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

713

dccg401_disable_dpstreamclk(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

714

dccg401_disable_dpstreamclk(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

715

dccg401_disable_dpstreamclk(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

718

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

719

dccg401_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

720

dccg401_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

721

dccg401_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

722

dccg401_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

726

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

728

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

762

void dccg401_set_ref_dscclk(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

765

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

78

void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

797

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

799

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

80

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

806

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

813

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

82

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

820

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

827

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

83

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

833

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

835

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

889

struct dccg *dccg401_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

896

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

98

dcn401_set_dppclk_enable(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

193

void dccg401_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

195

void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

196

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

200

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

205

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

209

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

211

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

212

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

213

void dccg401_set_ref_dscclk(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

216

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

219

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

224

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

229

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

231

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

232

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

234

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

237

struct dccg *dccg401_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

244

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1104

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1105

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1113

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1114

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1142

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1170

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1174

if (dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1175

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1176

dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1178

if (dccg && dccg->funcs->set_dtbclk_dto)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1179

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1182

} else if (dccg && dccg->funcs->disable_symclk_se) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1183

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1848

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1877

if (dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1878

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1955

dc->res_pool->dccg->funcs->get_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1956

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2394

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2397

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2398

dc->res_pool->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2885

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2888

if (dccg)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2889

dccg->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2890

dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2899

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2903

if (dccg)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2904

dccg->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2905

dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1782

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1783

dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1796

if (res_pool->dccg && res_pool->hubbub) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1798

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1890

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1891

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3034

if (dc->res_pool->dccg)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3035

dc->res_pool->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3036

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1673

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1681

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2203

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2226

if (dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2227

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2804

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2866

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2870

if (dccg && dccg->funcs->set_dtbclk_dto)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2871

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3019

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3035

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3037

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3041

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3043

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3046

if (dccg->funcs->enable_symclk_se && link_enc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3050

if (dccg->funcs->disable_symclk_se)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3051

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3054

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3059

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3060

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3061

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3130

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3131

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3146

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3147

dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

362

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

363

dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

838

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

839

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

840

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

881

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

885

if (dccg->funcs->set_dtbclk_p_src)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

886

dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

893

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

234

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

235

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

247

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

370

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

371

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

91

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

92

return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1255

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1281

if (dccg)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1282

if (dccg->funcs->dccg_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1283

dccg->funcs->dccg_read_reg_state(dccg, out_data->dccg_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

58

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

59

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

656

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

657

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

688

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

804

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

805

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

130

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

131

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

141

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

250

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

251

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

292

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

294

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

295

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

335

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

336

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

337

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

238

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

240

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

241

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

289

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

290

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

291

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

426

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

461

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

462

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

463

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1027

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1037

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1076

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1086

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1278

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

800

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

801

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

824

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

966

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

967

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1325

if (dc->res_pool->dccg->funcs->enable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1326

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1328

if (dc->res_pool->dccg->funcs->disable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1329

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

163

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

164

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

174

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

289

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

290

dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

486

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

487

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

488

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

497

if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

498

hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

499

hws->ctx->dc->res_pool->dccg, dp_hpo_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

508

if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

509

hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

510

hws->ctx->dc->res_pool->dccg, phy_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

162

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

163

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1648

bool should_use_dto_dscclk = (dc->res_pool->dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1659

hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1677

hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

186

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2033

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2034

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

334

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

335

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3485

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3512

if (dccg && dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3513

hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3594

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3607

hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

791

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

792

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

793

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

809

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

811

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

962

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

978

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

980

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

982

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

985

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

990

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

991

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

992

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1724

struct dccg *dccg, int inst, int num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1862

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1908

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

221

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

625

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

631

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

316

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

361

struct dccg;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

363

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

350

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

214

void (*update_dpp_dto)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

217

void (*get_dccg_ref_freq)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

220

void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

222

void (*otg_add_pixel)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

224

void (*otg_drop_pixel)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

226

void (*dccg_init)(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

227

void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

228

void (*allow_clock_gating)(struct dccg *dccg, bool allow);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

229

void (*enable_memory_low_power)(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

230

bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

232

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

237

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

243

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

248

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

252

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

257

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

261

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

266

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

272

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

277

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

281

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

285

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

289

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

293

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

296

void (*set_pixel_rate_div)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

301

void (*get_pixel_rate_div)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

307

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

313

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

316

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

321

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

326

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

330

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

333

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

336

void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

337

void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

338

void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

339

void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

340

void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

118

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

119

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

120

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

142

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

143

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

144

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

813

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

823

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

848

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

855

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

934

if (dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

935

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1218

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1219

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2563

pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2564

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1011

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1012

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1223

pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1224

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1537

pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1538

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

788

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

789

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1221

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1222

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2466

pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2467

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1189

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1190

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1582

pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1583

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1141

if (pool->dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1142

dcn_dccg_destroy(&pool->dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1381

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1382

if (pool->dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1085

if (pool->dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1086

dcn_dccg_destroy(&pool->dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1313

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1314

if (pool->dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1523

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1524

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2077

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2078

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1581

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1582

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2002

pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2003

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1524

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1525

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2026

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2027

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1516

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1517

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1901

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1902

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1524

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1525

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2387

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2388

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1504

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1505

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1886

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1887

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1594

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1595

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2039

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2040

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1574

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1575

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2011

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2012

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1581

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1582

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2018

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2019

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1530

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1531

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2087

pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2088

if (pool->base.dccg == NULL) {