cx18_av_read4
reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
v = cx18_av_read4(cx, CXADEC_HOST_REG1);
state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
(cx18_av_read4(cx, addr) & and_mask) |
u32 cx18_av_read4(struct cx18 *cx, u16 addr);
value = cx18_av_read4(cx, CXADEC_DL_CTL);
v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);