drivers/gpu/drm/amd/display/dc/dc.h

1632

struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/dc.h

1704

struct dc_lane_settings bios_forced_drive_settings;

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1435

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

284

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1110

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

623

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c

65

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {}

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

141

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

65

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

224

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

54

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

82

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

161

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

179

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

30

const struct dc_lane_settings *hw_lane_settings)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

303

struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

306

struct dc_lane_settings max_requested;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

356

const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

681

struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

856

struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

114

struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

161

const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/include/link_service_types.h

114

struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];