dbg_reg
u64 *dbg_reg)
val = *dbg_reg;
*dbg_reg = val;
u64 *dbg_reg)
p->regval = (*dbg_reg & mask) >> shift;
struct debug_reg dbg_reg;
*val = get_reg_val(id, vcpu->arch.dbg_reg.iac1);
*val = get_reg_val(id, vcpu->arch.dbg_reg.iac2);
*val = get_reg_val(id, vcpu->arch.dbg_reg.iac3);
*val = get_reg_val(id, vcpu->arch.dbg_reg.iac4);
*val = get_reg_val(id, vcpu->arch.dbg_reg.dac1);
*val = get_reg_val(id, vcpu->arch.dbg_reg.dac2);
vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val);
static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg,
dbg_reg->dbcr0 |= DBCR0_IAC1;
dbg_reg->iac1 = addr;
dbg_reg->dbcr0 |= DBCR0_IAC2;
dbg_reg->iac2 = addr;
dbg_reg->dbcr0 |= DBCR0_IAC3;
dbg_reg->iac3 = addr;
dbg_reg->dbcr0 |= DBCR0_IAC4;
dbg_reg->iac4 = addr;
dbg_reg->dbcr0 |= DBCR0_IDM;
static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
dbg_reg->dbcr0 |= DBCR0_DAC1R;
dbg_reg->dbcr0 |= DBCR0_DAC1W;
dbg_reg->dac1 = addr;
dbg_reg->dbcr0 |= DBCR0_DAC2R;
dbg_reg->dbcr0 |= DBCR0_DAC2W;
dbg_reg->dac2 = addr;
dbg_reg->dbcr0 |= DBCR0_IDM;
struct debug_reg *dbg_reg;
vcpu->arch.dbg_reg.dbcr0 = 0;
vcpu->arch.dbg_reg.dbcr0 = 0;
vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
dbg_reg = &(vcpu->arch.dbg_reg);
dbg_reg->dbcr1 = 0;
dbg_reg->dbcr2 = 0;
dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US |
dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++))
if (kvmppc_booke_add_watchpoint(dbg_reg, addr,
debug = vcpu->arch.dbg_reg;
current->thread.debug = vcpu->arch.dbg_reg;
struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg);
(vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM))
run->debug.arch.address = dbg_reg->dac1;
run->debug.arch.address = dbg_reg->dac2;
vcpu->arch.dbg_reg.iac1 = spr_val;
vcpu->arch.dbg_reg.iac2 = spr_val;
vcpu->arch.dbg_reg.iac3 = spr_val;
vcpu->arch.dbg_reg.iac4 = spr_val;
vcpu->arch.dbg_reg.dac1 = spr_val;
vcpu->arch.dbg_reg.dac2 = spr_val;
vcpu->arch.dbg_reg.dbcr0 = spr_val;
vcpu->arch.dbg_reg.dbcr1 = spr_val;
vcpu->arch.dbg_reg.dbcr2 = spr_val;
current->thread.debug = vcpu->arch.dbg_reg;
switch_booke_debug_regs(&vcpu->arch.dbg_reg);
*spr_val = vcpu->arch.dbg_reg.iac1;
*spr_val = vcpu->arch.dbg_reg.iac2;
*spr_val = vcpu->arch.dbg_reg.iac3;
*spr_val = vcpu->arch.dbg_reg.iac4;
*spr_val = vcpu->arch.dbg_reg.dac1;
*spr_val = vcpu->arch.dbg_reg.dac2;
*spr_val = vcpu->arch.dbg_reg.dbcr0;
*spr_val = vcpu->arch.dbg_reg.dbcr1;
*spr_val = vcpu->arch.dbg_reg.dbcr2;
dbg_reg(dev, priv, REGCTL1);
dbg_reg(dev, priv, REGCTL2);
dbg_reg(dev, priv, INTERRUPT_THRES);
dbg_reg(dev, priv, INTERRUPT_MASK);
dbg_reg(dev, priv, INTERRUPT_STATUS);
dbg_reg(dev, priv, CONTROLLER_STATUS);
dbg_reg(dev, priv, FIFO_DATA);
dbg_reg(dev, priv, ANALOG_CONTROL);
dbg_reg(dev, priv, AUX_DATA);
dbg_reg(dev, priv, DEBOUNCE_CNTR_STAT);
dbg_reg(dev, priv, SCAN_CNTR_STAT);
dbg_reg(dev, priv, REM_CNTR_STAT);
dbg_reg(dev, priv, SETTLING_TIMER_STAT);
dbg_reg(dev, priv, SPARE_REG);
dbg_reg(dev, priv, SOFT_BYPASS_CONTROL);
dbg_reg(dev, priv, SOFT_BYPASS_DATA);
dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
dbg_reg("reg #%02d == 0x%08x", address, value);
dbg_reg("reg #%02d <- 0x%08x", address, value);
dbg_reg("reg #%02d == 0x%08x", address, value);
dbg_reg("reg #%02d <- 0x%08x", address, value);
dbg_reg("reg #%02d |= 0x%08x (old =0x%08x)", address, mask, reg);
dbg_reg("reg #%02d &= 0x%08x (old = 0x%08x, mask = 0x%08x)",
unsigned int dbg_reg, reg_offset;
dbg_reg = AR_DMADBG_4;
dbg_reg = AR_DMADBG_5;
dma_dbg_chain = REG_READ(ah, dbg_reg);