crypto/ecc.c

1016

const struct ecc_curve *curve)

crypto/ecc.c

1020

vli_mult(product, left, right, curve->g.ndigits);

crypto/ecc.c

1021

vli_mmod_fast(result, product, curve);

crypto/ecc.c

1026

const struct ecc_curve *curve)

crypto/ecc.c

1030

vli_square(product, left, curve->g.ndigits);

crypto/ecc.c

1031

vli_mmod_fast(result, product, curve);

crypto/ecc.c

1130

const struct ecc_curve *curve)

crypto/ecc.c

1135

const u64 *curve_prime = curve->p;

crypto/ecc.c

1136

const unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

1142

vli_mod_square_fast(t4, y1, curve);

crypto/ecc.c

1144

vli_mod_mult_fast(t5, x1, t4, curve);

crypto/ecc.c

1146

vli_mod_square_fast(t4, t4, curve);

crypto/ecc.c

1148

vli_mod_mult_fast(y1, y1, z1, curve);

crypto/ecc.c

1150

vli_mod_square_fast(z1, z1, curve);

crypto/ecc.c

1159

vli_mod_mult_fast(x1, x1, z1, curve);

crypto/ecc.c

1176

vli_mod_square_fast(z1, x1, curve);

crypto/ecc.c

1184

vli_mod_mult_fast(x1, x1, t5, curve);

crypto/ecc.c

1194

static void apply_z(u64 *x1, u64 *y1, u64 *z, const struct ecc_curve *curve)

crypto/ecc.c

1198

vli_mod_square_fast(t1, z, curve); /* z^2 */

crypto/ecc.c

1199

vli_mod_mult_fast(x1, x1, t1, curve); /* x1 * z^2 */

crypto/ecc.c

1200

vli_mod_mult_fast(t1, t1, z, curve); /* z^3 */

crypto/ecc.c

1201

vli_mod_mult_fast(y1, y1, t1, curve); /* y1 * z^3 */

crypto/ecc.c

1206

u64 *p_initial_z, const struct ecc_curve *curve)

crypto/ecc.c

1209

const unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

1220

apply_z(x1, y1, z, curve);

crypto/ecc.c

1222

ecc_point_double_jacobian(x1, y1, z, curve);

crypto/ecc.c

1224

apply_z(x2, y2, z, curve);

crypto/ecc.c

1232

const struct ecc_curve *curve)

crypto/ecc.c

1236

const u64 *curve_prime = curve->p;

crypto/ecc.c

1237

const unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

1242

vli_mod_square_fast(t5, t5, curve);

crypto/ecc.c

1244

vli_mod_mult_fast(x1, x1, t5, curve);

crypto/ecc.c

1246

vli_mod_mult_fast(x2, x2, t5, curve);

crypto/ecc.c

1250

vli_mod_square_fast(t5, y2, curve);

crypto/ecc.c

1259

vli_mod_mult_fast(y1, y1, x2, curve);

crypto/ecc.c

1263

vli_mod_mult_fast(y2, y2, x2, curve);

crypto/ecc.c

1275

const struct ecc_curve *curve)

crypto/ecc.c

1281

const u64 *curve_prime = curve->p;

crypto/ecc.c

1282

const unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

1287

vli_mod_square_fast(t5, t5, curve);

crypto/ecc.c

1289

vli_mod_mult_fast(x1, x1, t5, curve);

crypto/ecc.c

1291

vli_mod_mult_fast(x2, x2, t5, curve);

crypto/ecc.c

1300

vli_mod_mult_fast(y1, y1, t6, curve);

crypto/ecc.c

1304

vli_mod_square_fast(x2, y2, curve);

crypto/ecc.c

1311

vli_mod_mult_fast(y2, y2, t7, curve);

crypto/ecc.c

1316

vli_mod_square_fast(t7, t5, curve);

crypto/ecc.c

1322

vli_mod_mult_fast(t6, t6, t5, curve);

crypto/ecc.c

1331

u64 *initial_z, const struct ecc_curve *curve,

crypto/ecc.c

1339

u64 *curve_prime = curve->p;

crypto/ecc.c

1344

carry = vli_add(sk[0], scalar, curve->n, ndigits);

crypto/ecc.c

1345

vli_add(sk[1], sk[0], curve->n, ndigits);

crypto/ecc.c

1347

if (curve->nbits == 521) /* NIST P521 */

crypto/ecc.c

1348

num_bits = curve->nbits + 2;

crypto/ecc.c

1355

xycz_initial_double(rx[1], ry[1], rx[0], ry[0], initial_z, curve);

crypto/ecc.c

1359

xycz_add_c(rx[1 - nb], ry[1 - nb], rx[nb], ry[nb], curve);

crypto/ecc.c

1360

xycz_add(rx[nb], ry[nb], rx[1 - nb], ry[1 - nb], curve);

crypto/ecc.c

1364

xycz_add_c(rx[1 - nb], ry[1 - nb], rx[nb], ry[nb], curve);

crypto/ecc.c

1370

vli_mod_mult_fast(z, z, ry[1 - nb], curve);

crypto/ecc.c

1372

vli_mod_mult_fast(z, z, point->x, curve);

crypto/ecc.c

1378

vli_mod_mult_fast(z, z, point->y, curve);

crypto/ecc.c

1380

vli_mod_mult_fast(z, z, rx[1 - nb], curve);

crypto/ecc.c

1383

xycz_add(rx[nb], ry[nb], rx[1 - nb], ry[1 - nb], curve);

crypto/ecc.c

1385

apply_z(rx[0], ry[0], z, curve);

crypto/ecc.c

1394

const struct ecc_curve *curve)

crypto/ecc.c

1399

unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

1403

vli_mod_sub(z, result->x, p->x, curve->p, ndigits);

crypto/ecc.c

1406

xycz_add(px, py, result->x, result->y, curve);

crypto/ecc.c

1407

vli_mod_inv(z, z, curve->p, ndigits);

crypto/ecc.c

1408

apply_z(result->x, result->y, z, curve);

crypto/ecc.c

1417

const struct ecc_curve *curve)

crypto/ecc.c

1423

unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

1431

ecc_point_add(&sum, p, q, curve);

crypto/ecc.c

1449

ecc_point_double_jacobian(rx, ry, z, curve);

crypto/ecc.c

1460

apply_z(tx, ty, z, curve);

crypto/ecc.c

1461

vli_mod_sub(tz, rx, tx, curve->p, ndigits);

crypto/ecc.c

1462

xycz_add(tx, ty, rx, ry, curve);

crypto/ecc.c

1463

vli_mod_mult_fast(z, z, tz, curve);

crypto/ecc.c

1466

vli_mod_inv(z, z, curve->p, ndigits);

crypto/ecc.c

1467

apply_z(rx, ry, z, curve);

crypto/ecc.c

1477

static int __ecc_is_key_valid(const struct ecc_curve *curve,

crypto/ecc.c

1486

if (curve->g.ndigits != ndigits)

crypto/ecc.c

1492

vli_sub(res, curve->n, one, ndigits);

crypto/ecc.c

1504

const struct ecc_curve *curve = ecc_get_curve(curve_id);

crypto/ecc.c

1511

return __ecc_is_key_valid(curve, private_key, ndigits);

crypto/ecc.c

1525

const struct ecc_curve *curve = ecc_get_curve(curve_id);

crypto/ecc.c

1527

unsigned int nbits = vli_num_bits(curve->n, ndigits);

crypto/ecc.c

1554

if (__ecc_is_key_valid(curve, private_key, ndigits))

crypto/ecc.c

1566

const struct ecc_curve *curve = ecc_get_curve(curve_id);

crypto/ecc.c

1579

ecc_point_mult(pk, &curve->g, private_key, NULL, curve, ndigits);

crypto/ecc.c

1582

if (ecc_is_pubkey_valid_full(curve, pk)) {

crypto/ecc.c

1598

int ecc_is_pubkey_valid_partial(const struct ecc_curve *curve,

crypto/ecc.c

1603

if (WARN_ON(pk->ndigits != curve->g.ndigits))

crypto/ecc.c

1611

if (vli_cmp(curve->p, pk->x, pk->ndigits) != 1)

crypto/ecc.c

1613

if (vli_cmp(curve->p, pk->y, pk->ndigits) != 1)

crypto/ecc.c

1617

vli_mod_square_fast(yy, pk->y, curve); /* y^2 */

crypto/ecc.c

1618

vli_mod_square_fast(xxx, pk->x, curve); /* x^2 */

crypto/ecc.c

1619

vli_mod_mult_fast(xxx, xxx, pk->x, curve); /* x^3 */

crypto/ecc.c

1620

vli_mod_mult_fast(w, curve->a, pk->x, curve); /* a·x */

crypto/ecc.c

1621

vli_mod_add(w, w, curve->b, curve->p, pk->ndigits); /* a·x + b */

crypto/ecc.c

1622

vli_mod_add(w, w, xxx, curve->p, pk->ndigits); /* x^3 + a·x + b */

crypto/ecc.c

1631

int ecc_is_pubkey_valid_full(const struct ecc_curve *curve,

crypto/ecc.c

1637

int ret = ecc_is_pubkey_valid_partial(curve, pk);

crypto/ecc.c

1647

ecc_point_mult(nQ, pk, curve->n, NULL, curve, pk->ndigits);

crypto/ecc.c

1665

const struct ecc_curve *curve = ecc_get_curve(curve_id);

crypto/ecc.c

1684

ret = ecc_is_pubkey_valid_partial(curve, pk);

crypto/ecc.c

1694

ecc_point_mult(product, pk, private_key, rand_z, curve, ndigits);

crypto/ecc.c

957

const struct ecc_curve *curve)

crypto/ecc.c

960

const u64 *curve_prime = curve->p;

crypto/ecc.c

961

const unsigned int ndigits = curve->g.ndigits;

crypto/ecc.c

964

if (strncmp(curve->name, "nist_", 5) != 0) {

crypto/ecdsa.c

114

ctx->curve->g.ndigits);

crypto/ecdsa.c

144

if (ndigits != ctx->curve->g.ndigits)

crypto/ecdsa.c

15

const struct ecc_curve *curve;

crypto/ecdsa.c

152

ret = ecc_is_pubkey_valid_full(ctx->curve, &ctx->pub_key);

crypto/ecdsa.c

170

return ctx->curve->nbits;

crypto/ecdsa.c

25

const struct ecc_curve *curve = ctx->curve;

crypto/ecdsa.c

26

unsigned int ndigits = curve->g.ndigits;

crypto/ecdsa.c

35

if (vli_is_zero(r, ndigits) || vli_cmp(r, curve->n, ndigits) >= 0 ||

crypto/ecdsa.c

36

vli_is_zero(s, ndigits) || vli_cmp(s, curve->n, ndigits) >= 0)

crypto/ecdsa.c

44

vli_mod_inv(s1, s, curve->n, ndigits);

crypto/ecdsa.c

46

vli_mod_mult_slow(u1, hash, s1, curve->n, ndigits);

crypto/ecdsa.c

48

vli_mod_mult_slow(u2, r, s1, curve->n, ndigits);

crypto/ecdsa.c

50

ecc_point_mult_shamir(&res, u1, &curve->g, u2, &ctx->pub_key, curve);

crypto/ecdsa.c

53

if (unlikely(vli_cmp(res.x, curve->n, ndigits) == 1))

crypto/ecdsa.c

55

vli_sub(res.x, res.x, curve->n, ndigits);

crypto/ecdsa.c

71

size_t bufsize = ctx->curve->g.ndigits * sizeof(u64);

crypto/ecdsa.c

84

ecc_digits_from_bytes(digest, bufsize, hash, ctx->curve->g.ndigits);

crypto/ecdsa.c

92

ctx->curve = ecc_get_curve(curve_id);

crypto/ecdsa.c

93

if (!ctx->curve)

crypto/ecrdsa.c

108

vli_cmp(r, ctx->curve->n, ndigits) >= 0 ||

crypto/ecrdsa.c

110

vli_cmp(s, ctx->curve->n, ndigits) >= 0)

crypto/ecrdsa.c

116

if (vli_cmp(e, ctx->curve->n, ndigits) >= 0)

crypto/ecrdsa.c

117

vli_sub(e, e, ctx->curve->n, ndigits);

crypto/ecrdsa.c

122

vli_mod_inv(v, e, ctx->curve->n, ndigits);

crypto/ecrdsa.c

125

vli_mod_mult_slow(z1, s, v, ctx->curve->n, ndigits);

crypto/ecrdsa.c

126

vli_sub(_r, ctx->curve->n, r, ndigits);

crypto/ecrdsa.c

127

vli_mod_mult_slow(z2, _r, v, ctx->curve->n, ndigits);

crypto/ecrdsa.c

130

ecc_point_mult_shamir(&cc, z1, &ctx->curve->g, z2, &ctx->pub_key,

crypto/ecrdsa.c

131

ctx->curve);

crypto/ecrdsa.c

132

if (vli_cmp(cc.x, ctx->curve->n, ndigits) >= 0)

crypto/ecrdsa.c

133

vli_sub(cc.x, cc.x, ctx->curve->n, ndigits);

crypto/ecrdsa.c

150

ctx->curve = get_curve_by_oid(ctx->curve_oid);

crypto/ecrdsa.c

220

if (!ctx->curve ||

crypto/ecrdsa.c

221

ctx->curve->g.ndigits * sizeof(u64) != ctx->digest_len)

crypto/ecrdsa.c

229

ctx->key_len != ctx->curve->g.ndigits * sizeof(u64) * 2)

crypto/ecrdsa.c

238

if (ecc_is_pubkey_valid_partial(ctx->curve, &ctx->pub_key))

crypto/ecrdsa.c

37

const struct ecc_curve *curve; /* curve from oid */

crypto/ecrdsa.c

90

if (!ctx->curve ||

crypto/ecrdsa.c

96

dlen != ctx->curve->g.ndigits * sizeof(u64) ||

crypto/ecrdsa.c

97

ctx->pub_key.ndigits != ctx->curve->g.ndigits ||

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1234

const struct ecc_curve *curve = ecc_get_curve(ctx->curve_id);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1237

if (unlikely(!curve))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1244

fill_curve_param(p, curve->p, cur_sz, curve->g.ndigits);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1245

fill_curve_param(a, curve->a, cur_sz, curve->g.ndigits);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1246

fill_curve_param(b, curve->b, cur_sz, curve->g.ndigits);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1247

fill_curve_param(x, curve->g.x, cur_sz, curve->g.ndigits);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1248

fill_curve_param(y, curve->g.y, cur_sz, curve->g.ndigits);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1249

fill_curve_param(n, curve->n, cur_sz, curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

101

const struct ecc_curve *curve;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

224

const struct ecc_curve *curve)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

227

u32 op_size = (curve->g.ndigits > ECC_CURVE_NIST_P256_DIGITS) ?

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

229

size_t nbytes = digits_to_bytes(curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

270

curve->p, nbytes);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

274

curve->a, nbytes);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

302

const struct ecc_curve *curve,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

328

curve->p, nbytes);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

345

const struct ecc_curve *curve,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

353

if (WARN_ON(pk->ndigits != curve->g.ndigits))

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

361

if (vli_cmp(curve->p, pk->x, pk->ndigits) != 1)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

364

if (vli_cmp(curve->p, pk->y, pk->ndigits) != 1)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

371

rc = kmb_ecc_do_scalar_op(ecc_dev, yy, pk->y, pk->y, curve, pk->ndigits,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

380

rc = kmb_ecc_do_scalar_op(ecc_dev, xxx, pk->x, w, curve, pk->ndigits,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

386

rc = kmb_ecc_do_scalar_op(ecc_dev, w, curve->a, pk->x, curve,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

393

rc = kmb_ecc_do_scalar_op(ecc_dev, w, w, curve->b, curve,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

400

rc = kmb_ecc_do_scalar_op(ecc_dev, w, xxx, w, curve, pk->ndigits,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

420

const struct ecc_curve *curve,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

427

rc = kmb_ocs_ecc_is_pubkey_valid_partial(ecc_dev, curve, pk);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

436

rc = kmb_ecc_point_mult(ecc_dev, nQ, pk, curve->n, curve);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

449

static int kmb_ecc_is_key_valid(const struct ecc_curve *curve,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

452

size_t ndigits = curve->g.ndigits;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

466

vli_sub(res, curve->n, one, ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

486

static int kmb_ecc_gen_privkey(const struct ecc_curve *curve, u64 *privkey)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

488

size_t nbytes = digits_to_bytes(curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

493

nbits = vli_num_bits(curve->n, curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

496

if (nbits < 160 || curve->g.ndigits > ARRAY_SIZE(priv))

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

514

rc = kmb_ecc_is_key_valid(curve, priv, nbytes);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

518

ecc_swap_digits(priv, privkey, curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

538

if (params.key_size > digits_to_bytes(tctx->curve->g.ndigits)) {

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

545

rc = kmb_ecc_gen_privkey(tctx->curve, tctx->private_key);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

549

rc = kmb_ecc_is_key_valid(tctx->curve, (const u64 *)params.key,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

555

tctx->curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

560

tctx->curve = NULL;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

570

const struct ecc_curve *curve = tctx->curve;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

577

nbytes = digits_to_bytes(curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

590

pk = ecc_alloc_point(curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

594

ecc_swap_digits(pubk_buf, pk->x, curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

595

ecc_swap_digits(&pubk_buf[curve->g.ndigits], pk->y, curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

603

rc = kmb_ocs_ecc_is_pubkey_valid_partial(ecc_dev, curve, pk);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

615

rc = kmb_ecc_point_mult(ecc_dev, result, pk, tctx->private_key, curve);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

652

const struct ecc_curve *curve = tctx->curve;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

660

pubk_len = 2 * digits_to_bytes(curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

662

pk = ecc_alloc_point(curve->g.ndigits);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

667

rc = kmb_ecc_point_mult(tctx->ecc_dev, pk, &curve->g, tctx->private_key,

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

668

curve);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

673

if (kmb_ocs_ecc_is_pubkey_valid_full(tctx->ecc_dev, curve, pk)) {

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

717

const struct ecc_curve *curve = tctx->curve;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

720

if (!tctx->curve)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

728

if (req->dst_len < (2 * digits_to_bytes(curve->g.ndigits)))

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

742

const struct ecc_curve *curve = tctx->curve;

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

745

if (!tctx->curve)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

760

if (req->src_len != 2 * digits_to_bytes(curve->g.ndigits))

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

779

tctx->curve = ecc_get_curve(curve_id);

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

780

if (!tctx->curve)

drivers/crypto/intel/keembay/keembay-ocs-ecc.c

812

return digits_to_bytes(tctx->curve->g.ndigits) * 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1498

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1514

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1517

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1518

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1519

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1520

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1521

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1524

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1525

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1526

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1527

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1528

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1531

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1532

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1533

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1534

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1535

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1538

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1539

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1540

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1541

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1542

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1545

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1546

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1547

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1548

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1549

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1552

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1553

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1554

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1555

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1556

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1559

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1560

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1561

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1562

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1563

curve += 2;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1566

REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1567

REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1568

REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1569

REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

133

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

192

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

198

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

204

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

210

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

216

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

226

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

231

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

237

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

243

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

249

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

258

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

263

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

269

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

275

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

281

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

290

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

295

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

301

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

307

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

313

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

322

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

327

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

333

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

339

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

345

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

354

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

359

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

365

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

371

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

377

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

386

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

391

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

397

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

403

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

409

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

418

curve += 2;

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

423

curve[0].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

429

curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

435

curve[1].offset,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

441

curve[1].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

634

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

659

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

661

CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

662

CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

663

CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

664

CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

666

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

668

CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

669

CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

670

CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

671

CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

673

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

675

CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

676

CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

677

CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

678

CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

680

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

682

CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

683

CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

684

CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

685

CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

687

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

689

CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

690

CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

691

CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

692

CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

694

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

696

CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

697

CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

698

CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

699

CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

701

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

703

CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

704

CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

705

CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

706

CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

708

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

710

CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

711

CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

712

CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

713

CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

715

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

717

CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

718

CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

719

CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

720

CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

722

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

724

CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

725

CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

726

CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

727

CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

729

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

731

CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

732

CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

733

CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

734

CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

736

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

738

CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

739

CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

740

CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

741

CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

743

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

745

CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

746

CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

747

CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

748

CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

750

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

752

CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

753

CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

754

CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

755

CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

757

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

759

CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

760

CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

761

CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

762

CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

764

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

766

CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

767

CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

768

CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

769

CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

771

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

773

CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

774

CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

775

CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

776

CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

784

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

809

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

811

CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

812

CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

813

CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

814

CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

816

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

818

CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

819

CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

820

CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

821

CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

823

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

825

CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

826

CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

827

CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

828

CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

830

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

832

CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

833

CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

834

CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

835

CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

837

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

839

CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

840

CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

841

CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

842

CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

844

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

846

CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

847

CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

848

CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

849

CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

851

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

853

CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

854

CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

855

CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

856

CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

858

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

860

CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

861

CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

862

CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

863

CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

865

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

867

CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

868

CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

869

CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

870

CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

872

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

874

CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

875

CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

876

CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

877

CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

879

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

881

CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

882

CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

883

CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

884

CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

886

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

888

CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

889

CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

890

CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

891

CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

893

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

895

CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

896

CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

897

CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

898

CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

900

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

902

CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

903

CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

904

CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

905

CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

907

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

909

CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

910

CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

911

CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

912

CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

914

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

916

CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

917

CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

918

CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

919

CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

921

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

923

CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

924

CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

925

CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

926

CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1000

CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1002

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1004

CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1005

CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1006

CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1007

CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1009

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1011

CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1012

CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1013

CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1014

CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1016

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1018

CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1019

CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1020

CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1021

CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1023

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1025

CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1026

CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1027

CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1028

CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1030

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1032

CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1033

CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1034

CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1035

CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1037

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1039

CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1040

CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1041

CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1042

CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1044

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1046

CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1047

CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1048

CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1049

CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1051

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1053

CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1054

CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1055

CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1056

CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1058

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1060

CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1061

CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1062

CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1063

CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1065

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1067

CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1068

CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1069

CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1070

CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1078

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1103

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1105

CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1106

CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1107

CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1108

CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1110

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1112

CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1113

CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1114

CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1115

CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1117

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1119

CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1120

CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1121

CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1122

CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1124

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1126

CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1127

CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1128

CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1129

CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1131

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1133

CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1134

CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1135

CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1136

CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1138

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1140

CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1141

CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1142

CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1143

CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1145

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1147

CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1148

CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1149

CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1150

CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1152

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1154

CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1155

CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1156

CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1157

CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1159

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1161

CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1162

CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1163

CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1164

CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1166

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1168

CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1169

CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1170

CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1171

CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1173

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1175

CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1176

CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1177

CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1178

CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1180

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1182

CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1183

CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1184

CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1185

CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1187

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1189

CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1190

CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1191

CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1192

CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1194

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1196

CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1197

CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1198

CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1199

CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1201

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1203

CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1204

CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1205

CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1206

CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1208

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1210

CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1211

CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1212

CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1213

CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1215

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1217

CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1218

CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1219

CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1220

CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

928

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

953

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

955

CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

956

CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

957

CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

958

CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

960

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

962

CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

963

CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

964

CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

965

CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

967

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

969

CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

970

CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

971

CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

972

CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

974

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

976

CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

977

CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

978

CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

979

CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

981

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

983

CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

984

CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

985

CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

986

CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

988

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

990

CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

991

CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

992

CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

993

CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

995

curve += 2;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

997

CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

998

CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

999

CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

491

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

514

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

516

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

517

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

518

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

519

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

521

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

523

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

524

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

525

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

526

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

528

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

530

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

531

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

532

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

533

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

535

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

537

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

538

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

539

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

540

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

542

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

544

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

545

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

546

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

547

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

549

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

551

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

552

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

553

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

554

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

556

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

558

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

559

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

560

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

561

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

563

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

565

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

566

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

567

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

568

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

571

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

573

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

574

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

575

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

576

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

578

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

580

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

581

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

582

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

583

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

585

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

587

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

588

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

589

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

590

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

592

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

594

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

595

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

596

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

597

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

599

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

601

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

602

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

603

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

604

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

606

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

608

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

609

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

610

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

611

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

613

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

615

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

616

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

617

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

618

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

620

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

622

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

623

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

624

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

625

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

627

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

629

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

630

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

631

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

632

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

640

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

663

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

665

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

666

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

667

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

668

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

670

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

672

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

673

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

674

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

675

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

678

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

680

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

681

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

682

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

683

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

685

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

687

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

688

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

689

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

690

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

692

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

694

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

695

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

696

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

697

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

699

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

701

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

702

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

703

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

704

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

706

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

708

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

709

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

710

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

711

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

713

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

715

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

716

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

717

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

718

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

721

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

723

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

724

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

725

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

726

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

728

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

730

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

731

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

732

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

733

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

735

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

737

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

738

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

739

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

740

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

742

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

744

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

745

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

746

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

747

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

749

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

751

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

752

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

753

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

754

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

756

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

758

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

759

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

760

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

761

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

763

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

765

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

766

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

767

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

768

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

770

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

772

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

773

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

774

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

775

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

777

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

779

MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

780

MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

781

MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

782

MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

348

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

371

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

372

if (curve) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

374

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

375

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

376

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

377

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

379

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

381

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

382

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

383

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

384

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

386

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

388

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

389

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

390

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

391

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

393

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

395

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

396

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

397

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

398

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

400

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

402

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

403

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

404

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

405

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

407

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

409

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

410

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

411

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

412

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

414

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

416

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

417

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

418

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

419

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

421

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

423

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

424

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

425

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

426

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

429

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

431

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

432

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

433

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

434

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

436

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

438

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

439

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

440

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

441

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

443

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

445

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

446

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

447

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

448

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

450

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

452

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

453

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

454

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

455

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

457

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

459

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

460

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

461

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

462

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

464

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

466

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

467

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

468

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

469

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

471

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

473

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

474

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

475

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

476

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

478

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

480

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

481

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

482

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

483

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

485

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

487

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

488

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

489

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

490

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

500

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

523

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

524

if (curve) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

526

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

527

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

528

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

529

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

531

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

533

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

534

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

535

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

536

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

539

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

541

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

542

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

543

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

544

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

546

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

548

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

549

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

550

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

551

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

553

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

555

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

556

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

557

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

558

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

560

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

562

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

563

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

564

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

565

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

567

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

569

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

570

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

571

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

572

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

574

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

576

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

577

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

578

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

579

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

582

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

584

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

585

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

586

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

587

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

589

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

591

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

592

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

593

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

594

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

596

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

598

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

599

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

600

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

601

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

603

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

605

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

606

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

607

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

608

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

610

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

612

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

613

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

614

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

615

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

617

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

619

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

620

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

621

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

622

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

624

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

626

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

627

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

628

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

629

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

631

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

633

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

634

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

635

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

636

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

638

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

640

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

641

MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

642

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

643

MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

271

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

294

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

295

if (curve) {

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

297

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

298

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

299

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

300

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

302

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

304

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

305

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

306

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

307

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

309

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

311

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

312

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

313

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

314

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

316

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

318

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

319

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

320

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

321

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

323

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

325

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

326

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

327

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

328

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

330

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

332

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

333

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

334

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

335

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

337

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

339

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

340

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

341

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

342

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

344

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

346

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

347

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

348

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

349

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

352

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

354

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

355

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

356

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

357

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

359

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

361

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

362

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

363

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

364

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

366

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

368

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

369

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

370

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

371

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

373

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

375

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

376

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

377

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

378

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

380

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

382

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

383

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

384

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

385

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

387

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

389

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

390

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

391

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

392

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

394

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

396

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

397

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

398

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

399

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

401

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

403

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

404

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

405

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

406

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

408

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

410

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

411

MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

412

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

413

MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

423

const struct gamma_curve *curve;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

446

curve = params->arr_curve_points;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

447

if (curve) {

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

449

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

450

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

451

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

452

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

454

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

456

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

457

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

458

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

459

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

462

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

464

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

465

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

466

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

467

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

469

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

471

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

472

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

473

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

474

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

476

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

478

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

479

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

480

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

481

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

483

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

485

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

486

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

487

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

488

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

490

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

492

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

493

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

494

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

495

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

497

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

499

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

500

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

501

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

502

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

504

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

506

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

507

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

508

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

509

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

511

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

513

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

514

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

515

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

516

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

518

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

520

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

521

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

522

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

523

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

525

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

527

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

528

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

529

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

530

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

532

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

534

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

535

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

536

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

537

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

539

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

541

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

542

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

543

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

544

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

546

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

548

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

549

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

550

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

551

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

553

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

555

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

556

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

557

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

558

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

560

curve += 2;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

562

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

563

MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

564

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

565

MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1181

static bool build_degamma(struct pwl_float_data_ex *curve,

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1202

curve[i].r = dc_fixpt_zero;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1203

curve[i].g = dc_fixpt_zero;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1204

curve[i].b = dc_fixpt_zero;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1209

curve[i].r = translate_to_linear_space_ex(

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1211

curve[i].g = curve[i].r;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1212

curve[i].b = curve[i].r;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1216

curve[i].r = dc_fixpt_one;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1217

curve[i].g = dc_fixpt_one;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1218

curve[i].b = dc_fixpt_one;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1679

struct pwl_float_data_ex *curve = NULL;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1741

curve = kvzalloc_objs(*curve, MAX_HW_POINTS + _EXTRA_POINTS);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1742

if (!curve)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1752

build_de_pq(curve,

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1760

build_degamma(curve,

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1765

build_hlg_degamma(curve,

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1773

curve[i].r = coordinates_x[i].x;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1774

curve[i].g = curve[i].r;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1775

curve[i].b = curve[i].r;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1788

struct pwl_float_data_ex *curvePt = curve;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1801

coordinates_x, axis_x, curve,

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1817

kvfree(curve);

drivers/hwmon/nzxt-kraken3.c

465

priv->channel_info[channel].mode = curve;

drivers/hwmon/nzxt-kraken3.c

499

if (priv->channel_info[dev_attr->nr].mode == curve) {

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

1264

unsigned int addr, const u8 *curve)

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

1284

val |= (*curve++ & 0x1f) << (i * 5);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

1294

const u32 curve[RKISP1_CIF_ISP_COMPAND_NUM_POINTS])

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

1298

rkisp1_write(params->rkisp1, reg_data, curve[i]);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2078

const struct rkisp1_ext_params_compand_curve_config *curve =

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2081

if (curve->header.flags & RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE) {

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2087

rkisp1_compand_expand_config(params, &curve->config);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2089

if ((curve->header.flags & RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE) &&

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2090

!(params->enabled_blocks & BIT(curve->header.type)))

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2098

const struct rkisp1_ext_params_compand_curve_config *curve =

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2101

if (curve->header.flags & RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE) {

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2107

rkisp1_compand_compress_config(params, &curve->config);

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2109

if ((curve->header.flags & RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE) &&

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

2110

!(params->enabled_blocks & BIT(curve->header.type)))

include/crypto/internal/ecc.h

160

int ecc_is_pubkey_valid_partial(const struct ecc_curve *curve,

include/crypto/internal/ecc.h

174

int ecc_is_pubkey_valid_full(const struct ecc_curve *curve,

include/crypto/internal/ecc.h

308

const struct ecc_curve *curve);