davinci_nand_readl
val = davinci_nand_readl(info, NRCSR_OFFSET);
return davinci_nand_readl(info, NANDF1ECC_OFFSET
nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
val = davinci_nand_readl(info, NANDFCR_OFFSET);
code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
davinci_nand_readl(info, NANDFSR_OFFSET);
davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
ecc_state = (davinci_nand_readl(info,
u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
error_address = davinci_nand_readl(info,
error_value = davinci_nand_readl(info,
error_address = davinci_nand_readl(info,
error_value = davinci_nand_readl(info,
davinci_nand_readl(info, 0);
val = davinci_nand_readl(info, NANDFCR_OFFSET);