arch/loongarch/include/asm/loongarch.h

1345

#define write_csr_entryhi(val) csr_write(val, LOONGARCH_CSR_TLBEHI)

arch/loongarch/include/asm/loongarch.h

1347

#define write_csr_entrylo0(val) csr_write(val, LOONGARCH_CSR_TLBELO0)

arch/loongarch/include/asm/loongarch.h

1349

#define write_csr_entrylo1(val) csr_write(val, LOONGARCH_CSR_TLBELO1)

arch/loongarch/include/asm/loongarch.h

1360

#define write_csr_prcfg1(val) csr_write(val, LOONGARCH_CSR_PRCFG1)

arch/loongarch/include/asm/loongarch.h

1362

#define write_csr_prcfg2(val) csr_write(val, LOONGARCH_CSR_PRCFG2)

arch/loongarch/include/asm/loongarch.h

1364

#define write_csr_prcfg3(val) csr_write(val, LOONGARCH_CSR_PRCFG3)

arch/loongarch/include/asm/loongarch.h

1371

#define write_csr_impctl1(val) csr_write(val, LOONGARCH_CSR_IMPCTL1)

arch/loongarch/include/asm/loongarch.h

1372

#define write_csr_impctl2(val) csr_write(val, LOONGARCH_CSR_IMPCTL2)

arch/loongarch/include/asm/percpu.h

29

csr_write(off, PERCPU_BASE_KS);

arch/loongarch/kernel/time.c

102

csr_write(timer_config, LOONGARCH_CSR_TCFG);

arch/loongarch/kernel/time.c

141

csr_write(init_offset, LOONGARCH_CSR_CNTC);

arch/loongarch/kernel/time.c

57

csr_write(timer_config, LOONGARCH_CSR_TCFG);

arch/loongarch/kernel/time.c

74

csr_write(timer_config, LOONGARCH_CSR_TCFG);

arch/loongarch/kernel/time.c

89

csr_write(timer_config, LOONGARCH_CSR_TCFG);

arch/loongarch/kernel/traps.c

1149

csr_write(eentry, LOONGARCH_CSR_EENTRY);

arch/loongarch/kernel/traps.c

1150

csr_write(__pa(eentry), LOONGARCH_CSR_MERRENTRY);

arch/loongarch/kernel/traps.c

1151

csr_write(__pa(tlbrentry), LOONGARCH_CSR_TLBRENTRY);

arch/loongarch/mm/tlb.c

232

csr_write(pwctl0, LOONGARCH_CSR_PWCTL0);

arch/loongarch/mm/tlb.c

233

csr_write(pwctl1, LOONGARCH_CSR_PWCTL1);

arch/loongarch/mm/tlb.c

234

csr_write((long)swapper_pg_dir, LOONGARCH_CSR_PGDH);

arch/loongarch/mm/tlb.c

235

csr_write((long)invalid_pg_dir, LOONGARCH_CSR_PGDL);

arch/loongarch/mm/tlb.c

236

csr_write((long)smp_processor_id(), LOONGARCH_CSR_TMID);

arch/loongarch/power/hibernate.c

36

csr_write(saved_pcpu_base, PERCPU_BASE_KS);

arch/loongarch/power/suspend.c

49

csr_write(eentry, LOONGARCH_CSR_EENTRY);

arch/loongarch/power/suspend.c

50

csr_write(eentry, LOONGARCH_CSR_MERRENTRY);

arch/loongarch/power/suspend.c

51

csr_write(tlbrentry, LOONGARCH_CSR_TLBRENTRY);

arch/loongarch/power/suspend.c

53

csr_write(saved_regs.pgd, LOONGARCH_CSR_PGDL);

arch/loongarch/power/suspend.c

54

csr_write(saved_regs.kpgd, LOONGARCH_CSR_PGDH);

arch/loongarch/power/suspend.c

59

csr_write(saved_regs.pcpu_base, PERCPU_BASE_KS);

arch/riscv/include/asm/kvm_nacl.h

228

csr_write(__csr, __val); \

arch/riscv/include/asm/switch_to.h

81

csr_write(CSR_ENVCFG, envcfg);

arch/riscv/include/asm/vector.h

160

csr_write(CSR_STATUS, status);

arch/riscv/include/asm/vector.h

186

csr_write(CSR_VXRM, (src->vcsr >> CSR_VXRM_SHIFT) & CSR_VXRM_MASK);

arch/riscv/include/asm/vector.h

187

csr_write(CSR_VXSAT, src->vcsr & CSR_VXSAT_MASK);

arch/riscv/include/asm/vector.h

190

csr_write(CSR_STATUS, status);

arch/riscv/include/asm/vector.h

192

csr_write(CSR_VCSR, src->vcsr);

arch/riscv/kernel/process.c

130

csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32);

arch/riscv/kernel/process.c

134

csr_write(CSR_STATUS, tmp);

arch/riscv/kernel/suspend.c

46

csr_write(CSR_SCRATCH, 0);

arch/riscv/kernel/suspend.c

48

csr_write(CSR_ENVCFG, context->envcfg);

arch/riscv/kernel/suspend.c

49

csr_write(CSR_TVEC, context->tvec);

arch/riscv/kernel/suspend.c

50

csr_write(CSR_IE, context->ie);

arch/riscv/kernel/suspend.c

55

csr_write(CSR_STIMECMP, ULONG_MAX);

arch/riscv/kernel/suspend.c

56

csr_write(CSR_STIMECMPH, context->stimecmph);

arch/riscv/kernel/suspend.c

58

csr_write(CSR_STIMECMP, context->stimecmp);

arch/riscv/kernel/suspend.c

61

csr_write(CSR_SATP, context->satp);

arch/riscv/kernel/usercfi.c

104

csr_write(CSR_ENVCFG, task->thread.envcfg);

arch/riscv/kernel/usercfi.c

74

csr_write(CSR_ENVCFG, task->thread.envcfg);

arch/riscv/kvm/aia.c

147

csr_write(CSR_VSISELECT, csr->vsiselect);

arch/riscv/kvm/aia.c

148

csr_write(CSR_HVIPRIO1, csr->hviprio1);

arch/riscv/kvm/aia.c

149

csr_write(CSR_HVIPRIO2, csr->hviprio2);

arch/riscv/kvm/aia.c

151

csr_write(CSR_VSIEH, csr->vsieh);

arch/riscv/kvm/aia.c

152

csr_write(CSR_HVIPH, csr->hviph);

arch/riscv/kvm/aia.c

153

csr_write(CSR_HVIPRIO1H, csr->hviprio1h);

arch/riscv/kvm/aia.c

154

csr_write(CSR_HVIPRIO2H, csr->hviprio2h);

arch/riscv/kvm/aia.c

572

csr_write(CSR_HGEIE, -1UL);

arch/riscv/kvm/aia.c

574

csr_write(CSR_HGEIE, 0);

arch/riscv/kvm/aia.c

601

csr_write(CSR_HVICTL, aia_hvictl_value(false));

arch/riscv/kvm/aia.c

602

csr_write(CSR_HVIPRIO1, 0x0);

arch/riscv/kvm/aia.c

603

csr_write(CSR_HVIPRIO2, 0x0);

arch/riscv/kvm/aia.c

605

csr_write(CSR_HVIPH, 0x0);

arch/riscv/kvm/aia.c

606

csr_write(CSR_HIDELEGH, 0x0);

arch/riscv/kvm/aia.c

607

csr_write(CSR_HVIPRIO1H, 0x0);

arch/riscv/kvm/aia.c

608

csr_write(CSR_HVIPRIO2H, 0x0);

arch/riscv/kvm/aia.c

637

csr_write(CSR_HVICTL, aia_hvictl_value(false));

arch/riscv/kvm/aia_imsic.c

105

csr_write(CSR_VSISELECT, __c); \

arch/riscv/kvm/aia_imsic.c

144

csr_write(CSR_VSISELECT, __c); \

arch/riscv/kvm/aia_imsic.c

145

csr_write(CSR_VSIREG, __v); \

arch/riscv/kvm/aia_imsic.c

181

csr_write(CSR_VSISELECT, __c); \

arch/riscv/kvm/aia_imsic.c

384

csr_write(CSR_HSTATUS, new_hstatus);

arch/riscv/kvm/aia_imsic.c

418

csr_write(CSR_HSTATUS, old_hstatus);

arch/riscv/kvm/aia_imsic.c

419

csr_write(CSR_VSISELECT, old_vsiselect);

arch/riscv/kvm/aia_imsic.c

456

csr_write(CSR_HSTATUS, new_hstatus);

arch/riscv/kvm/aia_imsic.c

486

csr_write(CSR_HSTATUS, old_hstatus);

arch/riscv/kvm/aia_imsic.c

487

csr_write(CSR_VSISELECT, old_vsiselect);

arch/riscv/kvm/aia_imsic.c

533

csr_write(CSR_HSTATUS, new_hstatus);

arch/riscv/kvm/aia_imsic.c

546

csr_write(CSR_HSTATUS, old_hstatus);

arch/riscv/kvm/aia_imsic.c

547

csr_write(CSR_VSISELECT, old_vsiselect);

arch/riscv/kvm/aia_imsic.c

571

csr_write(CSR_HSTATUS, new_hstatus);

arch/riscv/kvm/aia_imsic.c

585

csr_write(CSR_HSTATUS, old_hstatus);

arch/riscv/kvm/aia_imsic.c

586

csr_write(CSR_VSISELECT, old_vsiselect);

arch/riscv/kvm/aia_imsic.c

65

csr_write(CSR_VSISELECT, __c); \

arch/riscv/kvm/gstage.c

483

csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);

arch/riscv/kvm/gstage.c

490

csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);

arch/riscv/kvm/gstage.c

497

csr_write(CSR_HGATP, HGATP_MODE_SV39X4 << HGATP_MODE_SHIFT);

arch/riscv/kvm/gstage.c

504

csr_write(CSR_HGATP, HGATP_MODE_SV32X4 << HGATP_MODE_SHIFT);

arch/riscv/kvm/gstage.c

515

csr_write(CSR_HGATP, 0);

arch/riscv/kvm/main.c

44

csr_write(CSR_HEDELEG, 0);

arch/riscv/kvm/main.c

45

csr_write(CSR_HIDELEG, 0);

arch/riscv/kvm/main.c

48

csr_write(CSR_HCOUNTEREN, 0x02);

arch/riscv/kvm/main.c

50

csr_write(CSR_HVIP, 0);

arch/riscv/kvm/main.c

67

csr_write(CSR_VSIE, 0);

arch/riscv/kvm/main.c

68

csr_write(CSR_HVIP, 0);

arch/riscv/kvm/main.c

69

csr_write(CSR_HEDELEG, 0);

arch/riscv/kvm/main.c

70

csr_write(CSR_HIDELEG, 0);

arch/riscv/kvm/tlb.c

107

csr_write(CSR_HGATP, hgatp);

arch/riscv/kvm/tlb.c

119

csr_write(CSR_HGATP, hgatp);

arch/riscv/kvm/tlb.c

147

csr_write(CSR_HGATP, hgatp);

arch/riscv/kvm/tlb.c

158

csr_write(CSR_HGATP, hgatp);

arch/riscv/kvm/vcpu.c

613

csr_write(CSR_VSSTATUS, csr->vsstatus);

arch/riscv/kvm/vcpu.c

614

csr_write(CSR_VSIE, csr->vsie);

arch/riscv/kvm/vcpu.c

615

csr_write(CSR_VSTVEC, csr->vstvec);

arch/riscv/kvm/vcpu.c

616

csr_write(CSR_VSSCRATCH, csr->vsscratch);

arch/riscv/kvm/vcpu.c

617

csr_write(CSR_VSEPC, csr->vsepc);

arch/riscv/kvm/vcpu.c

618

csr_write(CSR_VSCAUSE, csr->vscause);

arch/riscv/kvm/vcpu.c

619

csr_write(CSR_VSTVAL, csr->vstval);

arch/riscv/kvm/vcpu.c

620

csr_write(CSR_HVIP, csr->hvip);

arch/riscv/kvm/vcpu.c

621

csr_write(CSR_VSATP, csr->vsatp);

arch/riscv/kvm/vcpu_config.c

100

csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);

arch/riscv/kvm/vcpu_config.c

92

csr_write(CSR_HEDELEG, cfg->hedeleg);

arch/riscv/kvm/vcpu_config.c

93

csr_write(CSR_HIDELEG, cfg->hideleg);

arch/riscv/kvm/vcpu_config.c

94

csr_write(CSR_HENVCFG, cfg->henvcfg);

arch/riscv/kvm/vcpu_config.c

96

csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);

arch/riscv/kvm/vcpu_config.c

98

csr_write(CSR_HSTATEEN0, cfg->hstateen0);

arch/riscv/kvm/vcpu_exit.c

144

csr_write(CSR_STVEC, old_stvec);

arch/riscv/kvm/vcpu_exit.c

145

csr_write(CSR_HSTATUS, old_hstatus);

arch/riscv/kvm/vcpu_sbi_fwft.c

150

csr_write(CSR_HENVCFG, prev);

arch/riscv/kvm/vcpu_sbi_fwft.c

211

csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg);

arch/riscv/kvm/vcpu_timer.c

364

csr_write(CSR_VSTIMECMP, -1UL);

arch/riscv/kvm/vcpu_timer.c

366

csr_write(CSR_VSTIMECMPH, -1UL);

arch/riscv/kvm/vmid.c

29

csr_write(CSR_HGATP, (kvm_riscv_gstage_mode(kvm_riscv_gstage_max_pgd_levels) <<

arch/riscv/kvm/vmid.c

34

csr_write(CSR_HGATP, 0);

arch/riscv/mm/context.c

192

csr_write(CSR_SATP, virt_to_pfn(mm->pgd) |

arch/riscv/mm/context.c

203

csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | satp_mode);

arch/riscv/mm/context.c

234

csr_write(CSR_SATP, asid_bits);

arch/riscv/mm/context.c

237

csr_write(CSR_SATP, old);

arch/riscv/mm/init.c

1293

csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | satp_mode);

arch/riscv/mm/init.c

871

csr_write(CSR_SATP, identity_satp);

arch/riscv/mm/kasan_init.c

489

csr_write(CSR_SATP, PFN_DOWN(__pa(tmp_pg_dir)) | satp_mode);

arch/riscv/mm/kasan_init.c

534

csr_write(CSR_SATP, PFN_DOWN(__pa(swapper_pg_dir)) | satp_mode);

drivers/cache/ax45mp_cache.c

74

csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);

drivers/cache/ax45mp_cache.c

75

csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);

drivers/clocksource/timer-riscv.c

38

csr_write(CSR_STIMECMP, ULONG_MAX);

drivers/clocksource/timer-riscv.c

40

csr_write(CSR_STIMECMPH, ULONG_MAX);

drivers/clocksource/timer-riscv.c

53

csr_write(CSR_STIMECMP, ULONG_MAX);

drivers/clocksource/timer-riscv.c

54

csr_write(CSR_STIMECMPH, next_tval >> 32);

drivers/clocksource/timer-riscv.c

55

csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);

drivers/clocksource/timer-riscv.c

57

csr_write(CSR_STIMECMP, next_tval);

drivers/firmware/efi/libstub/loongarch.c

96

csr_write(CSR_DMW0_INIT, LOONGARCH_CSR_DMWIN0);

drivers/firmware/efi/libstub/loongarch.c

97

csr_write(CSR_DMW1_INIT, LOONGARCH_CSR_DMWIN1);

drivers/firmware/efi/libstub/loongarch.c

98

csr_write(CSR_DMW2_INIT, LOONGARCH_CSR_DMWIN2);

drivers/firmware/efi/libstub/loongarch.c

99

csr_write(CSR_DMW3_INIT, LOONGARCH_CSR_DMWIN3);

drivers/firmware/efi/libstub/riscv.c

96

csr_write(CSR_SATP, 0);

drivers/irqchip/irq-riscv-imsic-state.c

31

csr_write(CSR_ISELECT, reg);

drivers/irqchip/irq-riscv-imsic-state.c

32

csr_write(CSR_IREG, val);

drivers/irqchip/irq-riscv-imsic-state.c

37

csr_write(CSR_ISELECT, reg);

drivers/irqchip/irq-riscv-imsic-state.c

43

csr_write(CSR_ISELECT, reg);

drivers/irqchip/irq-riscv-imsic-state.c

49

csr_write(CSR_ISELECT, reg);

drivers/irqchip/irq-riscv-imsic-state.c

55

csr_write(CSR_ISELECT, reg);

drivers/perf/riscv_pmu_sbi.c

1157

csr_write(CSR_SCOUNTEREN, 0x7);

drivers/perf/riscv_pmu_sbi.c

1159

csr_write(CSR_SCOUNTEREN, 0x2);

drivers/perf/riscv_pmu_sbi.c

1183

csr_write(CSR_SCOUNTEREN, 0x0);

drivers/perf/riscv_pmu_sbi.c

1384

csr_write(CSR_SCOUNTEREN, 0x7);

drivers/perf/riscv_pmu_sbi.c

1386

csr_write(CSR_SCOUNTEREN, 0x2);

drivers/perf/riscv_pmu_sbi.c

785

csr_write(CSR_SCOUNTEREN,

drivers/perf/riscv_pmu_sbi.c

794

csr_write(CSR_SCOUNTEREN,

tools/testing/selftests/kvm/include/loongarch/arch_timer.h

41

csr_write(0, LOONGARCH_CSR_TCFG);

tools/testing/selftests/kvm/include/loongarch/arch_timer.h

50

csr_write(val, LOONGARCH_CSR_ECFG);

tools/testing/selftests/kvm/include/loongarch/arch_timer.h

59

csr_write(val, LOONGARCH_CSR_ECFG);

tools/testing/selftests/kvm/include/loongarch/arch_timer.h

70

csr_write(val, LOONGARCH_CSR_TCFG);

tools/testing/selftests/kvm/include/loongarch/pmu.h

54

csr_write(val, LOONGARCH_CSR_ECFG);

tools/testing/selftests/kvm/include/loongarch/pmu.h

63

csr_write(val, LOONGARCH_CSR_ECFG);

tools/testing/selftests/kvm/include/riscv/arch_timer.h

32

csr_write(CSR_STIMECMP, cval);

tools/testing/selftests/kvm/loongarch/arch_timer.c

24

csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR);

tools/testing/selftests/kvm/loongarch/arch_timer.c

44

csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR);

tools/testing/selftests/kvm/loongarch/arch_timer.c

61

csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR);

tools/testing/selftests/kvm/loongarch/pmu_test.c

119

csr_write(PMU_OVERFLOW - 1, LOONGARCH_CSR_PERFCNTR0);

tools/testing/selftests/kvm/loongarch/pmu_test.c

120

csr_write(PMU_ENVENT_ENABLED | CSR_PERFCTRL_PMIE | LOONGARCH_PMU_EVENT_CYCLES, LOONGARCH_CSR_PERFCTRL0);

tools/testing/selftests/kvm/loongarch/pmu_test.c

65

csr_write(0, LOONGARCH_CSR_PERFCNTR0);

tools/testing/selftests/kvm/loongarch/pmu_test.c

66

csr_write(0, LOONGARCH_CSR_PERFCNTR1);

tools/testing/selftests/kvm/loongarch/pmu_test.c

67

csr_write(0, LOONGARCH_CSR_PERFCNTR2);

tools/testing/selftests/kvm/loongarch/pmu_test.c

68

csr_write(0, LOONGARCH_CSR_PERFCNTR3);

tools/testing/selftests/kvm/loongarch/pmu_test.c

70

csr_write(PMU_ENVENT_ENABLED |

tools/testing/selftests/kvm/loongarch/pmu_test.c

73

csr_write(PMU_ENVENT_ENABLED |

tools/testing/selftests/kvm/loongarch/pmu_test.c

76

csr_write(PMU_ENVENT_ENABLED |

tools/testing/selftests/kvm/loongarch/pmu_test.c

79

csr_write(PMU_ENVENT_ENABLED |