d2l_write
d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
d2l_write(tc->i2c, PPI_LANEENABLE, val);
d2l_write(tc->i2c, DSI_LANEENABLE, val);
d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
d2l_write(tc->i2c, VPCTRL, val);
d2l_write(tc->i2c, HTIM1, htime1);
d2l_write(tc->i2c, VTIM1, vtime1);
d2l_write(tc->i2c, HTIM2, htime2);
d2l_write(tc->i2c, VTIM2, vtime2);
d2l_write(tc->i2c, VFUEN, VFUEN_EN);
d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5));
d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2));
d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1));
d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2));
d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4));
d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0));
d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0));
d2l_write(tc->i2c, VFUEN, VFUEN_EN);
d2l_write(tc->i2c, LVCFG, val);