drivers/crypto/ccree/cc_debugfs.c

13

.offset = CC_REG(_X) \

drivers/crypto/ccree/cc_driver.c

109

cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));

drivers/crypto/ccree/cc_driver.c

135

ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST));

drivers/crypto/ccree/cc_driver.c

194

irr = cc_ioread(drvdata, CC_REG(HOST_IRR));

drivers/crypto/ccree/cc_driver.c

200

imr = cc_ioread(drvdata, CC_REG(HOST_IMR));

drivers/crypto/ccree/cc_driver.c

203

cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);

drivers/crypto/ccree/cc_driver.c

211

cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask);

drivers/crypto/ccree/cc_driver.c

221

cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK);

drivers/crypto/ccree/cc_driver.c

231

axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));

drivers/crypto/ccree/cc_driver.c

260

val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));

drivers/crypto/ccree/cc_driver.c

280

val = cc_ioread(drvdata, CC_REG(AXIM_CFG));

drivers/crypto/ccree/cc_driver.c

281

cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);

drivers/crypto/ccree/cc_driver.c

283

cc_ioread(drvdata, CC_REG(AXIM_CFG)));

drivers/crypto/ccree/cc_driver.c

287

val = cc_ioread(drvdata, CC_REG(HOST_IRR));

drivers/crypto/ccree/cc_driver.c

289

cc_iowrite(drvdata, CC_REG(HOST_ICR), val);

drivers/crypto/ccree/cc_driver.c

297

cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);

drivers/crypto/ccree/cc_driver.c

299

cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params);

drivers/crypto/ccree/cc_driver.c

301

cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const);

drivers/crypto/ccree/cc_driver.c

329

new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);

drivers/crypto/ccree/cc_driver.c

330

new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);

drivers/crypto/ccree/cc_driver.c

331

new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);

drivers/crypto/ccree/cc_driver.c

333

new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);

drivers/crypto/ccree/cc_driver.c

334

new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);

drivers/crypto/ccree/cc_driver.c

335

new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);

drivers/crypto/ccree/cc_driver.c

436

val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));

drivers/crypto/ccree/cc_driver.c

454

val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));

drivers/crypto/ccree/cc_driver.c

55

CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1),

drivers/crypto/ccree/cc_driver.c

56

CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4)

drivers/crypto/ccree/cc_driver.c

580

cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);

drivers/crypto/ccree/cc_driver.c

60

CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1),

drivers/crypto/ccree/cc_driver.c

61

CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3)

drivers/crypto/ccree/cc_fips.c

126

val = (CC_REG(HOST_IMR) & ~irq);

drivers/crypto/ccree/cc_fips.c

127

cc_iowrite(drvdata, CC_REG(HOST_IMR), val);

drivers/crypto/ccree/cc_fips.c

26

reg = cc_ioread(drvdata, CC_REG(GPR_HOST));

drivers/crypto/ccree/cc_fips.c

49

cc_iowrite(drvdata, CC_REG(HOST_GPR0), val);

drivers/crypto/ccree/cc_pm.c

24

cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);

drivers/crypto/ccree/cc_pm.c

48

cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);

drivers/crypto/ccree/cc_request_mgr.c

146

CC_REG(DSCRPTR_QUEUE_SRAM_SIZE));

drivers/crypto/ccree/cc_request_mgr.c

188

void __iomem *reg = drvdata->cc_base + CC_REG(DSCRPTR_QUEUE_WORD0);

drivers/crypto/ccree/cc_request_mgr.c

248

cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));

drivers/crypto/ccree/cc_request_mgr.c

526

cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));

drivers/crypto/ccree/cc_request_mgr.c

627

cc_iowrite(drvdata, CC_REG(HOST_ICR), irq);

drivers/crypto/ccree/cc_request_mgr.c

638

drvdata->irq |= cc_ioread(drvdata, CC_REG(HOST_IRR));

drivers/crypto/ccree/cc_request_mgr.c

649

cc_iowrite(drvdata, CC_REG(HOST_ICR), irq);

drivers/crypto/ccree/cc_request_mgr.c

657

cc_iowrite(drvdata, CC_REG(HOST_IMR),

drivers/crypto/ccree/cc_request_mgr.c

658

cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~drvdata->comp_mask);

drivers/crypto/ccree/cc_sram_mgr.c

24

start = cc_ioread(drvdata, CC_REG(HOST_SEP_SRAM_THRESHOLD));