cx231xx_set_field
cx231xx_set_field
cx231xx_set_field
cx231xx_set_field
cx231xx_set_field
cx231xx_set_field
cx231xx_set_field
cx231xx_set_field
value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
cx231xx_set_field(FLD_SIF_EN, 1));
cx231xx_set_field(FLD_SIF_EN, 0));
cx231xx_set_field(FLD_ACFG_DIS, 1));
cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
cx231xx_set_field(FLD_ACFG_DIS, 1));
cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
cx231xx_set_field(FLD_ACFG_DIS, 1));
cx231xx_set_field(FLD_INPUT_MODE,
cx231xx_set_field(FLD_ACFG_DIS, 1));
cx231xx_set_field(FLD_INPUT_MODE,
cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
u32 cx231xx_set_field(u32 field_mask, u32 data);