cx18_write_reg_expect
cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE,
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
cx18_write_reg_expect(cx, x, reg,
cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
cx18_write_reg_expect(cx,
cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,
cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);
cx18_write_reg_expect(cx, dir_lo << 16,
cx18_write_reg_expect(cx, (dir_lo << 16) | val_lo,
cx18_write_reg_expect(cx, dir_hi << 16,
cx18_write_reg_expect(cx, (dir_hi << 16) | val_hi,
cx18_write_reg_expect(cx, 0x10000000, 0xc71004,
cx18_write_reg_expect(cx, 0x10001000, 0xc71024,
cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0);
cx18_write_reg_expect(cx, 0x00c000c0, 0xc7001c, 0x000000c0, 0x00c000c0);
cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0);
cx18_write_reg_expect(cx, HW2_I2C1_INT|HW2_I2C2_INT, HW2_INT_CLR_STATUS,
cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);