cx18_write_reg
cx18_write_reg(cx, x, reg);
cx18_write_reg(cx, value, 0xc40000 + addr);
cx18_write_reg(cx, v, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
cx18_write_reg(cx, r | SETSCL_BIT, addr);
cx18_write_reg(cx, r & ~SETSCL_BIT, addr);
cx18_write_reg(cx, r | SETSDL_BIT, addr);
cx18_write_reg(cx, r & ~SETSDL_BIT, addr);
cx18_write_reg(cx, 0x00c00000, 0xc730c8);
cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_1_WR);
cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_2_WR);
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_1_WR) | 4,
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_2_WR) | 4,
cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
cx18_write_reg(cx, val, 0xD000F8);
cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);