cx18_read_reg
u = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
u32 x = cx18_read_reg(cx, reg);
u32 x = cx18_read_reg(cx, reg);
u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
return cx18_read_reg(cx, 0xc40000 + addr);
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
devtype = cx18_read_reg(cx, 0xC72028);
v = cx18_read_reg(cx, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {
retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1;
(cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) {
cx18_read_reg(cx, CX18_REG_GPIO_DIR1),
cx18_read_reg(cx, CX18_REG_GPIO_DIR2),
cx18_read_reg(cx, CX18_REG_GPIO_OUT1),
cx18_read_reg(cx, CX18_REG_GPIO_OUT2));
u32 r = cx18_read_reg(cx, addr);
u32 r = cx18_read_reg(cx, addr);
return cx18_read_reg(cx, addr) & GETSCL_BIT;
return cx18_read_reg(cx, addr) & GETSDL_BIT;
if (cx18_read_reg(cx, CX18_REG_I2C_2_WR) != 0x0003c02f) {
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_1_WR) | 4,
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_2_WR) | 4,
cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
val = cx18_read_reg(cx, 0xD000F8);
sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;
sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;
hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;