arch/mips/cavium-octeon/executive/cvmx-boot-vector.c

147

cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);

arch/mips/cavium-octeon/executive/cvmx-boot-vector.c

148

cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);

arch/mips/cavium-octeon/executive/cvmx-boot-vector.c

150

cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8);

arch/mips/cavium-octeon/executive/cvmx-boot-vector.c

151

cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem);

arch/mips/cavium-octeon/executive/cvmx-boot-vector.c

152

cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);

arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c

257

cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff);

arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c

140

cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c

69

cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c

96

cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-loop.c

62

cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-loop.c

68

cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-npi.c

94

cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

109

cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

110

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

111

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

112

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

114

cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

116

cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

118

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

120

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

138

cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

140

cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

142

cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

144

cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

180

cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

184

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

207

cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

218

cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

220

cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

224

cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

226

cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

229

cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

231

cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

245

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

318

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

326

cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

332

cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

340

cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

350

cvmx_write_csr(CVMX_NPI_DBG_SELECT,

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

359

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

386

cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

387

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

388

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

390

cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

391

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

392

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

394

cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

395

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

396

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

418

cvmx_write_csr(CVMX_GMXX_TXX_CLK

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

428

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

431

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

438

cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

439

cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS,

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

444

cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

448

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

103

cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

118

cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

153

cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

172

cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

214

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

257

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

258

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

265

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

266

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

273

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

274

cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

281

cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

285

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

292

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

353

cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

378

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

62

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

82

cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-spi.c

118

cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-spi.c

89

cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

107

cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

116

cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

147

cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

158

cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

164

cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

191

cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

211

cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

242

cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

273

cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

100

cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

128

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

136

cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

140

cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

142

cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

144

cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

153

cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

165

cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

186

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

204

cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

205

cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

206

cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

207

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

210

cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

212

cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

214

cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

231

cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

232

cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

233

cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

237

cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

241

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

285

cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

286

cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

287

cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

78

cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);

arch/mips/cavium-octeon/executive/cvmx-helper.c

1035

cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);

arch/mips/cavium-octeon/executive/cvmx-helper.c

659

cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);

arch/mips/cavium-octeon/executive/cvmx-helper.c

672

cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64);

arch/mips/cavium-octeon/executive/cvmx-helper.c

822

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);

arch/mips/cavium-octeon/executive/cvmx-helper.c

844

cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)),

arch/mips/cavium-octeon/executive/cvmx-helper.c

902

cvmx_write_csr(CVMX_GMXX_PRTX_CFG

arch/mips/cavium-octeon/executive/cvmx-helper.c

905

cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),

arch/mips/cavium-octeon/executive/cvmx-helper.c

907

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),

arch/mips/cavium-octeon/executive/cvmx-helper.c

910

cvmx_write_csr(CVMX_GMXX_RXX_JABBER

arch/mips/cavium-octeon/executive/cvmx-helper.c

913

cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX

arch/mips/cavium-octeon/executive/cvmx-helper.c

945

cvmx_write_csr(CVMX_GMXX_PRTX_CFG

arch/mips/cavium-octeon/executive/cvmx-helper.c

948

cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),

arch/mips/cavium-octeon/executive/cvmx-helper.c

950

cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),

arch/mips/cavium-octeon/executive/cvmx-helper.c

952

cvmx_write_csr(CVMX_GMXX_RXX_JABBER

arch/mips/cavium-octeon/executive/cvmx-helper.c

955

cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX

arch/mips/cavium-octeon/executive/cvmx-helper.c

958

cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

229

cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

239

cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block),

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

272

cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

281

cvmx_write_csr(CVMX_PCSXX_INT_REG(index),

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

302

cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

312

cvmx_write_csr(CVMX_SPXX_INT_REG(index),

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

343

cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

352

cvmx_write_csr(CVMX_STXX_INT_REG(index),

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

377

cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

56

cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

137

cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

69

cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

102

cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

119

cvmx_write_csr(CVMX_L2C_SPAR0,

arch/mips/cavium-octeon/executive/cvmx-l2c.c

124

cvmx_write_csr(CVMX_L2C_SPAR1,

arch/mips/cavium-octeon/executive/cvmx-l2c.c

129

cvmx_write_csr(CVMX_L2C_SPAR2,

arch/mips/cavium-octeon/executive/cvmx-l2c.c

134

cvmx_write_csr(CVMX_L2C_SPAR3,

arch/mips/cavium-octeon/executive/cvmx-l2c.c

154

cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

156

cvmx_write_csr(CVMX_L2C_SPAR4,

arch/mips/cavium-octeon/executive/cvmx-l2c.c

201

cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

228

cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),

arch/mips/cavium-octeon/executive/cvmx-l2c.c

365

cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

372

cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

376

cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

390

cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

397

cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

402

cvmx_write_csr(CVMX_L2C_DBG, 0);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

907

cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

915

cvmx_write_csr(CVMX_L2C_DBG, 0);

arch/mips/cavium-octeon/executive/cvmx-pko.c

107

cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

133

cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

154

cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

198

cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

220

cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);

arch/mips/cavium-octeon/executive/cvmx-pko.c

222

cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);

arch/mips/cavium-octeon/executive/cvmx-pko.c

225

cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);

arch/mips/cavium-octeon/executive/cvmx-pko.c

227

cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);

arch/mips/cavium-octeon/executive/cvmx-pko.c

252

cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

263

cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

275

cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

300

cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

302

cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

529

cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

530

cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

590

cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

591

cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

629

cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);

arch/mips/cavium-octeon/executive/cvmx-pko.c

630

cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

208

cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);

arch/mips/cavium-octeon/executive/cvmx-spi.c

210

cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);

arch/mips/cavium-octeon/executive/cvmx-spi.c

213

cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);

arch/mips/cavium-octeon/executive/cvmx-spi.c

214

cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0);

arch/mips/cavium-octeon/executive/cvmx-spi.c

217

cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

238

cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

243

cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

248

cvmx_write_csr(CVMX_SPXX_INT_REG(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

250

cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

251

cvmx_write_csr(CVMX_STXX_INT_REG(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

253

cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

267

cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

272

cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

288

cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

291

cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

325

cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

339

cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

346

cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

362

cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

368

cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

373

cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

379

cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

387

cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

402

cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

409

cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

456

cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

481

cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

529

cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

535

cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

551

cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

589

cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

601

cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

643

cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

651

cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);

arch/mips/cavium-octeon/executive/cvmx-spi.c

657

cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

661

cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface),

arch/mips/cavium-octeon/executive/cvmx-spi.c

665

cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64);

arch/mips/cavium-octeon/executive/octeon-model.c

47

cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);

arch/mips/cavium-octeon/oct_ilm.c

132

cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);

arch/mips/cavium-octeon/oct_ilm.c

96

cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);

arch/mips/cavium-octeon/octeon-irq.c

1092

cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

1106

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);

arch/mips/cavium-octeon/octeon-irq.c

1399

cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);

arch/mips/cavium-octeon/octeon-irq.c

1400

cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);

arch/mips/cavium-octeon/octeon-irq.c

1401

cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);

arch/mips/cavium-octeon/octeon-irq.c

1402

cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);

arch/mips/cavium-octeon/octeon-irq.c

1422

cvmx_write_csr(base + regx + ipx, 0);

arch/mips/cavium-octeon/octeon-irq.c

1671

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1688

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1703

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1719

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1734

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1750

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1764

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1778

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1790

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1801

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1831

cvmx_write_csr(en_addr, mask);

arch/mips/cavium-octeon/octeon-irq.c

1850

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);

arch/mips/cavium-octeon/octeon-irq.c

2152

cvmx_write_csr(host_data->en_reg, en);

arch/mips/cavium-octeon/octeon-irq.c

2166

cvmx_write_csr(host_data->en_reg, en);

arch/mips/cavium-octeon/octeon-irq.c

2273

cvmx_write_csr(host_data->en_reg, en);

arch/mips/cavium-octeon/octeon-irq.c

2274

cvmx_write_csr(host_data->raw_reg, 1ull << i);

arch/mips/cavium-octeon/octeon-irq.c

2282

cvmx_write_csr(host_data->raw_reg, 1ull << i);

arch/mips/cavium-octeon/octeon-irq.c

2343

cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */

arch/mips/cavium-octeon/octeon-irq.c

2344

cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */

arch/mips/cavium-octeon/octeon-irq.c

2420

cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2426

cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);

arch/mips/cavium-octeon/octeon-irq.c

2443

cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2444

cvmx_write_csr(isc_ctl_addr, 0);

arch/mips/cavium-octeon/octeon-irq.c

2468

cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2484

cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2508

cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2537

cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2543

cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);

arch/mips/cavium-octeon/octeon-irq.c

2631

cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2686

cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2712

cvmx_write_csr(isc_w1s_addr, isc_w1s.u64);

arch/mips/cavium-octeon/octeon-irq.c

2732

cvmx_write_csr(isc_w1c_addr, isc_ctl.u64);

arch/mips/cavium-octeon/octeon-irq.c

2733

cvmx_write_csr(isc_ctl_addr, 0);

arch/mips/cavium-octeon/octeon-irq.c

2740

cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);

arch/mips/cavium-octeon/octeon-irq.c

2782

cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);

arch/mips/cavium-octeon/octeon-irq.c

2818

cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip2), 0);

arch/mips/cavium-octeon/octeon-irq.c

2819

cvmx_write_csr(b + CIU3_IDT_PP(idt_ip2, 0), 1ull << core);

arch/mips/cavium-octeon/octeon-irq.c

2820

cvmx_write_csr(b + CIU3_IDT_IO(idt_ip2), 0);

arch/mips/cavium-octeon/octeon-irq.c

2823

cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip3), 1);

arch/mips/cavium-octeon/octeon-irq.c

2824

cvmx_write_csr(b + CIU3_IDT_PP(idt_ip3, 0), 1ull << core);

arch/mips/cavium-octeon/octeon-irq.c

2825

cvmx_write_csr(b + CIU3_IDT_IO(idt_ip3), 0);

arch/mips/cavium-octeon/octeon-irq.c

2828

cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip4), 2);

arch/mips/cavium-octeon/octeon-irq.c

2829

cvmx_write_csr(b + CIU3_IDT_PP(idt_ip4, 0), 0);

arch/mips/cavium-octeon/octeon-irq.c

2830

cvmx_write_csr(b + CIU3_IDT_IO(idt_ip4), 0);

arch/mips/cavium-octeon/octeon-irq.c

2832

cvmx_write_csr(b + CIU3_IDT_CTL(unused_idt2), 0);

arch/mips/cavium-octeon/octeon-irq.c

2833

cvmx_write_csr(b + CIU3_IDT_PP(unused_idt2, 0), 0);

arch/mips/cavium-octeon/octeon-irq.c

2834

cvmx_write_csr(b + CIU3_IDT_IO(unused_idt2), 0);

arch/mips/cavium-octeon/octeon-irq.c

2839

cvmx_write_csr(b + CIU3_ISC_W1C(intsn), 2);

arch/mips/cavium-octeon/octeon-irq.c

2840

cvmx_write_csr(b + CIU3_ISC_CTL(intsn), 0);

arch/mips/cavium-octeon/octeon-irq.c

323

cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);

arch/mips/cavium-octeon/octeon-irq.c

332

cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

355

cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);

arch/mips/cavium-octeon/octeon-irq.c

364

cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

387

cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);

arch/mips/cavium-octeon/octeon-irq.c

396

cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

427

cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);

arch/mips/cavium-octeon/octeon-irq.c

429

cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

460

cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);

arch/mips/cavium-octeon/octeon-irq.c

462

cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

487

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

491

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

508

cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

524

cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

537

cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

552

cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask);

arch/mips/cavium-octeon/octeon-irq.c

571

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

575

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

590

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

594

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

611

cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

613

cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);

arch/mips/cavium-octeon/octeon-irq.c

635

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

642

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

665

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

672

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

706

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64);

arch/mips/cavium-octeon/octeon-irq.c

739

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);

arch/mips/cavium-octeon/octeon-irq.c

749

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);

arch/mips/cavium-octeon/octeon-irq.c

762

cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);

arch/mips/cavium-octeon/octeon-irq.c

839

cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);

arch/mips/cavium-octeon/octeon-irq.c

841

cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);

arch/mips/cavium-octeon/octeon-irq.c

874

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

877

cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

887

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

890

cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

917

cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);

arch/mips/cavium-octeon/octeon-irq.c

919

cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);

arch/mips/cavium-octeon/octeon-platform.c

110

cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);

arch/mips/cavium-octeon/octeon-platform.c

119

cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),

arch/mips/cavium-octeon/octeon-platform.c

140

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

159

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

191

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

195

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

198

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

208

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

218

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

222

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

232

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

239

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

246

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

253

cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

257

cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);

arch/mips/cavium-octeon/octeon-platform.c

313

cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);

arch/mips/cavium-octeon/octeon-platform.c

377

cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);

arch/mips/cavium-octeon/setup.c

1106

cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);

arch/mips/cavium-octeon/setup.c

211

cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);

arch/mips/cavium-octeon/setup.c

213

cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);

arch/mips/cavium-octeon/setup.c

281

cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);

arch/mips/cavium-octeon/setup.c

436

cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);

arch/mips/cavium-octeon/setup.c

438

cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);

arch/mips/cavium-octeon/setup.c

444

cvmx_write_csr(CVMX_RST_SOFT_RST, 1);

arch/mips/cavium-octeon/setup.c

446

cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);

arch/mips/cavium-octeon/setup.c

463

cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);

arch/mips/cavium-octeon/setup.c

480

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);

arch/mips/cavium-octeon/setup.c

481

cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);

arch/mips/cavium-octeon/setup.c

638

cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);

arch/mips/cavium-octeon/setup.c

649

cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);

arch/mips/cavium-octeon/setup.c

771

cvmx_write_csr(CVMX_LED_EN, 0);

arch/mips/cavium-octeon/setup.c

772

cvmx_write_csr(CVMX_LED_PRT, 0);

arch/mips/cavium-octeon/setup.c

773

cvmx_write_csr(CVMX_LED_DBG, 0);

arch/mips/cavium-octeon/setup.c

774

cvmx_write_csr(CVMX_LED_PRT_FMT, 0);

arch/mips/cavium-octeon/setup.c

775

cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);

arch/mips/cavium-octeon/setup.c

776

cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);

arch/mips/cavium-octeon/setup.c

777

cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);

arch/mips/cavium-octeon/setup.c

778

cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);

arch/mips/cavium-octeon/setup.c

779

cvmx_write_csr(CVMX_LED_EN, 1);

arch/mips/cavium-octeon/setup.c

850

cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);

arch/mips/cavium-octeon/setup.c

852

cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);

arch/mips/cavium-octeon/smp.c

107

cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);

arch/mips/cavium-octeon/smp.c

262

cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);

arch/mips/cavium-octeon/smp.c

339

cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);

arch/mips/cavium-octeon/smp.c

340

cvmx_write_csr(CVMX_CIU_PP_RST, 0);

arch/mips/cavium-octeon/smp.c

388

cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);

arch/mips/cavium-octeon/smp.c

389

cvmx_write_csr(CVMX_CIU_PP_RST, 0);

arch/mips/cavium-octeon/smp.c

398

cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);

arch/mips/cavium-octeon/smp.c

80

cvmx_write_csr(mbox_clrx, action);

arch/mips/include/asm/octeon/cvmx-fpa.h

165

cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,

arch/mips/include/asm/octeon/cvmx-fpa.h

176

cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

103

cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

107

cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

111

cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

115

cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

120

cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

142

cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

153

cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

204

cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

222

cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

249

cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

261

cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

279

cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

291

cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

307

cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

317

cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,

arch/mips/include/asm/octeon/cvmx-ipd.h

326

cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

334

cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

95

cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);

arch/mips/include/asm/octeon/cvmx-ipd.h

99

cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

296

cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

297

cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

327

cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

343

cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

357

cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

387

cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

470

cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

474

cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

493

cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);

arch/mips/include/asm/octeon/cvmx-pip.h

519

cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);

arch/mips/include/asm/octeon/cvmx-pko.h

585

cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);

arch/mips/include/asm/octeon/cvmx-pko.h

591

cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);

arch/mips/include/asm/octeon/cvmx-pko.h

598

cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);

arch/mips/include/asm/octeon/cvmx-pko.h

604

cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);

arch/mips/include/asm/octeon/cvmx-pko.h

610

cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);

arch/mips/include/asm/octeon/cvmx-pow.h

1857

cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);

arch/mips/include/asm/octeon/cvmx-pow.h

1907

cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);

arch/mips/include/asm/octeon/cvmx.h

282

cvmx_write_csr((__force uint64_t)csr_addr, val);

arch/mips/pci/msi-octeon.c

254

cvmx_write_csr(mis_ena_reg[irq_index], en);

arch/mips/pci/msi-octeon.c

270

cvmx_write_csr(mis_ena_reg[irq_index], en);

arch/mips/pci/msi-octeon.c

316

cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);

arch/mips/pci/pci-octeon.c

369

cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);

arch/mips/pci/pci-octeon.c

377

cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);

arch/mips/pci/pci-octeon.c

381

cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);

arch/mips/pci/pci-octeon.c

498

cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);

arch/mips/pci/pci-octeon.c

606

cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);

arch/mips/pci/pci-octeon.c

700

cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);

arch/mips/pci/pcie-octeon.c

1035

cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);

arch/mips/pci/pcie-octeon.c

1050

cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);

arch/mips/pci/pcie-octeon.c

1105

cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

1251

cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);

arch/mips/pci/pcie-octeon.c

1258

cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);

arch/mips/pci/pcie-octeon.c

1275

cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

1277

cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

1284

cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

1288

cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

1344

cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);

arch/mips/pci/pcie-octeon.c

1365

cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);

arch/mips/pci/pcie-octeon.c

1376

cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

1377

cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

1381

cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

1389

cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

1403

cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);

arch/mips/pci/pcie-octeon.c

1409

cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);

arch/mips/pci/pcie-octeon.c

1412

cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);

arch/mips/pci/pcie-octeon.c

1421

cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);

arch/mips/pci/pcie-octeon.c

1432

cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

1514

cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);

arch/mips/pci/pcie-octeon.c

1526

cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);

arch/mips/pci/pcie-octeon.c

178

cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);

arch/mips/pci/pcie-octeon.c

185

cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);

arch/mips/pci/pcie-octeon.c

207

cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);

arch/mips/pci/pcie-octeon.c

2079

cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);

arch/mips/pci/pcie-octeon.c

2086

cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);

arch/mips/pci/pcie-octeon.c

213

cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);

arch/mips/pci/pcie-octeon.c

452

cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);

arch/mips/pci/pcie-octeon.c

467

cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);

arch/mips/pci/pcie-octeon.c

471

cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);

arch/mips/pci/pcie-octeon.c

624

cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

630

cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

651

cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));

arch/mips/pci/pcie-octeon.c

751

cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);

arch/mips/pci/pcie-octeon.c

773

cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

776

cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

782

cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

785

cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

806

cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

808

cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

815

cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

819

cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);

arch/mips/pci/pcie-octeon.c

838

cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);

arch/mips/pci/pcie-octeon.c

892

cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);

arch/mips/pci/pcie-octeon.c

911

cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);

arch/mips/pci/pcie-octeon.c

921

cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

922

cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);

arch/mips/pci/pcie-octeon.c

926

cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

929

cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);

arch/mips/pci/pcie-octeon.c

959

cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);

arch/mips/pci/pcie-octeon.c

980

cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);

arch/mips/pci/pcie-octeon.c

991

cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);

drivers/ata/pata_octeon_cf.c

115

cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);

drivers/ata/pata_octeon_cf.c

204

cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);

drivers/ata/pata_octeon_cf.c

207

cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),

drivers/ata/pata_octeon_cf.c

279

cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);

drivers/ata/pata_octeon_cf.c

550

cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);

drivers/ata/pata_octeon_cf.c

553

cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);

drivers/ata/pata_octeon_cf.c

581

cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);

drivers/ata/pata_octeon_cf.c

614

cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);

drivers/ata/pata_octeon_cf.c

618

cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);

drivers/ata/pata_octeon_cf.c

622

cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);

drivers/ata/pata_octeon_cf.c

690

cvmx_write_csr(cf_port->dma_base + DMA_INT,

drivers/ata/pata_octeon_cf.c

983

cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);

drivers/ata/pata_octeon_cf.c

987

cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);

drivers/ata/pata_octeon_cf.c

991

cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);

drivers/char/hw_random/octeon-rng.c

36

cvmx_write_csr((unsigned long)p->control_status, ctl.u64);

drivers/char/hw_random/octeon-rng.c

47

cvmx_write_csr((unsigned long)p->control_status, ctl.u64);

drivers/edac/octeon_edac-l2c.c

100

cvmx_write_csr(CVMX_L2C_ERR_TDTX(tad), err_tdtx_reset.u64);

drivers/edac/octeon_edac-l2c.c

123

cvmx_write_csr(CVMX_L2C_ERR_TTGX(tad), err_ttgx_reset.u64);

drivers/edac/octeon_edac-l2c.c

160

cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);

drivers/edac/octeon_edac-l2c.c

165

cvmx_write_csr(CVMX_L2T_ERR, l2d_err.u64);

drivers/edac/octeon_edac-l2c.c

41

cvmx_write_csr(CVMX_L2T_ERR, l2t_err_reset.u64);

drivers/edac/octeon_edac-l2c.c

56

cvmx_write_csr(CVMX_L2D_ERR, l2d_err_reset.u64);

drivers/edac/octeon_edac-lmc.c

121

cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);

drivers/edac/octeon_edac-lmc.c

266

cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64);

drivers/edac/octeon_edac-lmc.c

298

cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);

drivers/edac/octeon_edac-lmc.c

68

cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64);

drivers/gpio/gpio-octeon.c

46

cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);

drivers/gpio/gpio-octeon.c

56

cvmx_write_csr(reg, mask);

drivers/gpio/gpio-octeon.c

72

cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1013

cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1022

cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1041

cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1047

cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1052

cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1071

cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1090

cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1105

cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1116

cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1124

cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1137

cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1144

cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1145

cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1146

cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1148

cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1149

cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1150

cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1153

cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR));

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1164

cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1169

cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1175

cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1204

cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1323

cvmx_write_csr(p->mix + MIX_ORING2, 1);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

165

cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

177

cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

249

cvmx_write_csr(p->mix + MIX_IRING2, 1);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

285

cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

302

cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

472

cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

524

cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

529

cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

611

cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

618

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

620

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

621

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

622

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

623

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

624

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

625

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

626

cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

630

cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

657

cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, max_packet);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

663

cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER,

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

678

cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

713

cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

728

cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

751

cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

772

cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

807

cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

830

cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

881

cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

900

cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64);

drivers/net/mdio/mdio-cavium.h

103

cvmx_write_csr((u64 __force)addr, val);

drivers/staging/octeon/ethernet-mdio.c

113

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);

drivers/staging/octeon/ethernet-rgmii.c

34

cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface),

drivers/staging/octeon/ethernet-rgmii.c

44

cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);

drivers/staging/octeon/ethernet-rgmii.c

49

cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),

drivers/staging/octeon/ethernet-rx.c

203

cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid),

drivers/staging/octeon/ethernet-rx.c

208

cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),

drivers/staging/octeon/ethernet-rx.c

234

cvmx_write_csr(CVMX_SSO_WQ_IQ_DIS,

drivers/staging/octeon/ethernet-rx.c

236

cvmx_write_csr(CVMX_SSO_WQ_INT,

drivers/staging/octeon/ethernet-rx.c

244

cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);

drivers/staging/octeon/ethernet-rx.c

390

cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), old_group_mask);

drivers/staging/octeon/ethernet-rx.c

393

cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);

drivers/staging/octeon/ethernet-rx.c

496

cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64);

drivers/staging/octeon/ethernet-rx.c

500

cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);

drivers/staging/octeon/ethernet-rx.c

508

cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), int_thr.u64);

drivers/staging/octeon/ethernet-rx.c

512

cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);

drivers/staging/octeon/ethernet-rx.c

533

cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), 0);

drivers/staging/octeon/ethernet-rx.c

535

cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), 0);

drivers/staging/octeon/ethernet-spi.c

100

cvmx_write_csr(CVMX_STXX_INT_MSK(index), 0);

drivers/staging/octeon/ethernet-spi.c

138

cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);

drivers/staging/octeon/ethernet-spi.c

149

cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);

drivers/staging/octeon/ethernet-spi.c

221

cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);

drivers/staging/octeon/ethernet-spi.c

222

cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);

drivers/staging/octeon/ethernet-spi.c

86

cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);

drivers/staging/octeon/ethernet-spi.c

93

cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);

drivers/staging/octeon/ethernet-spi.c

99

cvmx_write_csr(CVMX_SPXX_INT_MSK(index), 0);

drivers/staging/octeon/ethernet-tx.c

648

cvmx_write_csr(CVMX_CIU_TIMX(1), 0);

drivers/staging/octeon/ethernet-tx.c

659

cvmx_write_csr(CVMX_CIU_TIMX(1), 0);

drivers/staging/octeon/ethernet-tx.c

69

cvmx_write_csr(CVMX_CIU_TIMX(1), ciu_timx.u64);

drivers/staging/octeon/ethernet.c

160

cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);

drivers/staging/octeon/ethernet.c

261

cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface),

drivers/staging/octeon/ethernet.c

273

cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface),

drivers/staging/octeon/ethernet.c

281

cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface),

drivers/staging/octeon/ethernet.c

326

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),

drivers/staging/octeon/ethernet.c

329

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface),

drivers/staging/octeon/ethernet.c

332

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN

drivers/staging/octeon/ethernet.c

335

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN

drivers/staging/octeon/ethernet.c

338

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),

drivers/staging/octeon/ethernet.c

362

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),

drivers/staging/octeon/ethernet.c

365

cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);

drivers/staging/octeon/ethernet.c

366

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface),

drivers/staging/octeon/ethernet.c

368

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface),

drivers/staging/octeon/ethernet.c

370

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface),

drivers/staging/octeon/ethernet.c

372

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface),

drivers/staging/octeon/ethernet.c

374

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface),

drivers/staging/octeon/ethernet.c

376

cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface),

drivers/staging/octeon/ethernet.c

379

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),

drivers/staging/octeon/ethernet.c

471

cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);

drivers/staging/octeon/ethernet.c

655

cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, iface), delay_value);

drivers/staging/octeon/ethernet.c

659

cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, iface), delay_value);

drivers/staging/octeon/ethernet.c

748

cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),

drivers/usb/dwc3/dwc3-octeon.c

219

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);

drivers/usb/dwc3/dwc3-octeon.c

224

cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);

drivers/usb/dwc3/dwc3-octeon.c

229

cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);

drivers/usb/host/octeon-hcd.c

3629

cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64);

drivers/watchdog/octeon-wdt-main.c

579

cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);

drivers/watchdog/octeon-wdt-main.c

600

cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);