arch/mips/cavium-octeon/csrc-octeon.c

45

rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);

arch/mips/cavium-octeon/csrc-octeon.c

52

rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);

arch/mips/cavium-octeon/csrc-octeon.c

86

u64 clk_count = cvmx_read_csr(clk_reg);

arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c

165

status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);

arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c

260

debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);

arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c

264

debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);

arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c

276

cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS

arch/mips/cavium-octeon/executive/cvmx-helper-board.c

242

cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c

142

jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);

arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c

70

cvmx_read_csr(CVMX_CIU_QLM_JTGC);

arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c

98

jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);

arch/mips/cavium-octeon/executive/cvmx-helper-loop.c

59

port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));

arch/mips/cavium-octeon/executive/cvmx-helper-loop.c

66

ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);

arch/mips/cavium-octeon/executive/cvmx-helper-npi.c

91

cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

113

tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

115

tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

117

tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

168

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

203

cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

243

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

270

asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

314

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

319

cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

327

pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

336

gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

341

cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

360

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

402

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

425

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

432

cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 <<

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c

56

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

108

cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

113

cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

150

cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

211

gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

230

gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

237

cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

288

gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

351

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

376

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

416

cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

426

cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

433

cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

444

cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

454

cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

60

gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

70

cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

72

cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

98

cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-spi.c

116

port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));

arch/mips/cavium-octeon/executive/cvmx-helper-spi.c

87

enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

189

gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

209

gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

218

pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);

arch/mips/cavium-octeon/executive/cvmx-helper-util.c

252

gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

126

gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

134

xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

139

gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

141

gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

143

pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

149

gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

156

xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

184

gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

200

gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

211

cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

213

cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

215

cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

239

gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

271

gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

272

gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

274

cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

309

gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

310

gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

50

gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

76

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper.c

103

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));

arch/mips/cavium-octeon/executive/cvmx-helper.c

1032

l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);

arch/mips/cavium-octeon/executive/cvmx-helper.c

117

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface));

arch/mips/cavium-octeon/executive/cvmx-helper.c

129

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3));

arch/mips/cavium-octeon/executive/cvmx-helper.c

134

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));

arch/mips/cavium-octeon/executive/cvmx-helper.c

176

mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));

arch/mips/cavium-octeon/executive/cvmx-helper.c

178

mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));

arch/mips/cavium-octeon/executive/cvmx-helper.c

195

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));

arch/mips/cavium-octeon/executive/cvmx-helper.c

203

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));

arch/mips/cavium-octeon/executive/cvmx-helper.c

214

qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));

arch/mips/cavium-octeon/executive/cvmx-helper.c

224

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper.c

254

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper.c

333

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-helper.c

380

port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));

arch/mips/cavium-octeon/executive/cvmx-helper.c

381

tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));

arch/mips/cavium-octeon/executive/cvmx-helper.c

802

cvmx_read_csr(CVMX_GMXX_PRTX_CFG

arch/mips/cavium-octeon/executive/cvmx-helper.c

805

cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));

arch/mips/cavium-octeon/executive/cvmx-helper.c

807

cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));

arch/mips/cavium-octeon/executive/cvmx-helper.c

809

cvmx_read_csr(CVMX_GMXX_RXX_JABBER

arch/mips/cavium-octeon/executive/cvmx-helper.c

812

cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX

arch/mips/cavium-octeon/executive/cvmx-helper.c

828

wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);

arch/mips/cavium-octeon/executive/cvmx-helper.c

898

cvmx_read_csr(CVMX_GMXX_PRTX_CFG

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

240

cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

282

cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

313

cvmx_read_csr(CVMX_SPXX_INT_REG(index)));

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

353

cvmx_read_csr(CVMX_STXX_INT_REG(index)));

arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c

57

cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

65

csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));

arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c

83

mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

120

(cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |

arch/mips/cavium-octeon/executive/cvmx-l2c.c

125

(cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |

arch/mips/cavium-octeon/executive/cvmx-l2c.c

130

(cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |

arch/mips/cavium-octeon/executive/cvmx-l2c.c

135

(cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |

arch/mips/cavium-octeon/executive/cvmx-l2c.c

157

(cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

164

return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

166

return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

175

pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

210

l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

238

return cvmx_read_csr(CVMX_L2C_PFC0);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

244

counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

249

return cvmx_read_csr(CVMX_L2C_PFC1);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

255

counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

260

return cvmx_read_csr(CVMX_L2C_PFC2);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

266

counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

272

return cvmx_read_csr(CVMX_L2C_PFC3);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

278

counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

331

l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

362

l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

373

cvmx_read_csr(CVMX_L2C_DBG);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

377

cvmx_read_csr(CVMX_L2C_LCKOFF);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

379

if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {

arch/mips/cavium-octeon/executive/cvmx-l2c.c

392

cvmx_read_csr(CVMX_L2C_LCKBASE);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

399

cvmx_read_csr(CVMX_L2C_LCKBASE);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

403

cvmx_read_csr(CVMX_L2C_DBG);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

405

l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

58

return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

677

l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));

arch/mips/cavium-octeon/executive/cvmx-l2c.c

73

return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

738

l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

743

l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

75

return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

77

return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

79

return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

822

mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

845

l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

908

cvmx_read_csr(CVMX_L2C_DBG);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

916

cvmx_read_csr(CVMX_L2C_DBG);

arch/mips/cavium-octeon/executive/cvmx-pko.c

240

flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);

arch/mips/cavium-octeon/executive/cvmx-pko.c

261

pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);

arch/mips/cavium-octeon/executive/cvmx-pko.c

273

pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);

arch/mips/cavium-octeon/executive/cvmx-spi.c

207

spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

209

stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

219

spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

249

cvmx_read_csr(CVMX_SPXX_INT_REG(interface)));

arch/mips/cavium-octeon/executive/cvmx-spi.c

252

cvmx_read_csr(CVMX_STXX_INT_REG(interface)));

arch/mips/cavium-octeon/executive/cvmx-spi.c

449

stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

474

stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

533

spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

548

stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

586

srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

609

stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

641

srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));

arch/mips/cavium-octeon/executive/cvmx-spi.c

649

stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));

arch/mips/cavium-octeon/executive/octeon-model.c

414

if (cvmx_read_csr(CVMX_MIO_FUS_PDF) & (0x1ULL << 32))

arch/mips/cavium-octeon/executive/octeon-model.c

48

while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))

arch/mips/cavium-octeon/executive/octeon-model.c

75

l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3;

arch/mips/cavium-octeon/executive/octeon-model.c

76

fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);

arch/mips/cavium-octeon/executive/octeon-model.c

77

fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);

arch/mips/cavium-octeon/flash_setup.c

86

region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));

arch/mips/cavium-octeon/oct_ilm.c

134

timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));

arch/mips/cavium-octeon/oct_ilm.c

98

timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));

arch/mips/cavium-octeon/octeon-irq.c

1302

u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));

arch/mips/cavium-octeon/octeon-irq.c

1319

u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);

arch/mips/cavium-octeon/octeon-irq.c

1337

u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid));

arch/mips/cavium-octeon/octeon-irq.c

1338

u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid));

arch/mips/cavium-octeon/octeon-irq.c

1403

cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));

arch/mips/cavium-octeon/octeon-irq.c

1425

cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));

arch/mips/cavium-octeon/octeon-irq.c

2001

sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful;

arch/mips/cavium-octeon/octeon-irq.c

2008

src = cvmx_read_csr(src_reg);

arch/mips/cavium-octeon/octeon-irq.c

2027

cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);

arch/mips/cavium-octeon/octeon-irq.c

2029

cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id));

arch/mips/cavium-octeon/octeon-irq.c

2038

u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60;

arch/mips/cavium-octeon/octeon-irq.c

2054

cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);

arch/mips/cavium-octeon/octeon-irq.c

2056

cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id));

arch/mips/cavium-octeon/octeon-irq.c

2150

en = cvmx_read_csr(host_data->en_reg);

arch/mips/cavium-octeon/octeon-irq.c

2164

en = cvmx_read_csr(host_data->en_reg);

arch/mips/cavium-octeon/octeon-irq.c

2256

en = cvmx_read_csr(host_data->en_reg);

arch/mips/cavium-octeon/octeon-irq.c

2257

raw = cvmx_read_csr(host_data->raw_reg);

arch/mips/cavium-octeon/octeon-irq.c

2271

en = cvmx_read_csr(host_data->en_reg);

arch/mips/cavium-octeon/octeon-irq.c

2384

isc.u64 = cvmx_read_csr(ciu3_info->ciu3_addr + CIU3_ISC_CTL(hwirq));

arch/mips/cavium-octeon/octeon-irq.c

2427

cvmx_read_csr(isc_ctl_addr);

arch/mips/cavium-octeon/octeon-irq.c

2445

cvmx_read_csr(isc_ctl_addr);

arch/mips/cavium-octeon/octeon-irq.c

2469

cvmx_read_csr(isc_w1c_addr);

arch/mips/cavium-octeon/octeon-irq.c

2485

cvmx_read_csr(isc_w1c_addr);

arch/mips/cavium-octeon/octeon-irq.c

2509

cvmx_read_csr(isc_w1c_addr);

arch/mips/cavium-octeon/octeon-irq.c

2544

cvmx_read_csr(isc_ctl_addr);

arch/mips/cavium-octeon/octeon-irq.c

2605

dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(3 * cvmx_get_local_core_num()));

arch/mips/cavium-octeon/octeon-irq.c

2632

cvmx_read_csr(isc_w1c_addr);

arch/mips/cavium-octeon/octeon-irq.c

2672

dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(1 + 3 * core));

arch/mips/cavium-octeon/octeon-irq.c

2687

cvmx_read_csr(isc_w1c_addr);

arch/mips/cavium-octeon/octeon-irq.c

2713

cvmx_read_csr(isc_w1s_addr);

arch/mips/cavium-octeon/octeon-irq.c

2742

cvmx_read_csr(isc_ctl_addr);

arch/mips/cavium-octeon/octeon-irq.c

2783

cvmx_read_csr(isc_w1c_addr);

arch/mips/cavium-octeon/octeon-irq.c

2897

consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST);

arch/mips/cavium-octeon/octeon-platform.c

1045

mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));

arch/mips/cavium-octeon/octeon-platform.c

114

cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));

arch/mips/cavium-octeon/octeon-platform.c

124

clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));

arch/mips/cavium-octeon/octeon-platform.c

193

clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));

arch/mips/cavium-octeon/octeon-platform.c

301

ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));

arch/mips/cavium-octeon/octeon-platform.c

367

ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));

arch/mips/cavium-octeon/octeon-platform.c

42

clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));

arch/mips/cavium-octeon/octeon-platform.c

955

mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));

arch/mips/cavium-octeon/octeon-platform.c

978

cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));

arch/mips/cavium-octeon/setup.c

1102

lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));

arch/mips/cavium-octeon/setup.c

718

rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);

arch/mips/cavium-octeon/setup.c

723

rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);

arch/mips/cavium-octeon/setup.c

804

if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {

arch/mips/cavium-octeon/smp.c

72

action = cvmx_read_csr(mbox_clrx);

arch/mips/include/asm/octeon/cvmx-fpa.h

148

status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);

arch/mips/include/asm/octeon/cvmx-fpa.h

163

cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);

arch/mips/include/asm/octeon/cvmx-fpa.h

188

cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));

arch/mips/include/asm/octeon/cvmx-ipd.h

117

ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);

arch/mips/include/asm/octeon/cvmx-ipd.h

132

ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);

arch/mips/include/asm/octeon/cvmx-ipd.h

151

ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);

arch/mips/include/asm/octeon/cvmx-ipd.h

166

ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);

arch/mips/include/asm/octeon/cvmx-ipd.h

171

ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);

arch/mips/include/asm/octeon/cvmx-ipd.h

180

cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);

arch/mips/include/asm/octeon/cvmx-ipd.h

197

cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);

arch/mips/include/asm/octeon/cvmx-ipd.h

207

cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);

arch/mips/include/asm/octeon/cvmx-ipd.h

230

cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);

arch/mips/include/asm/octeon/cvmx-ipd.h

242

cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);

arch/mips/include/asm/octeon/cvmx-ipd.h

252

cvmx_read_csr

arch/mips/include/asm/octeon/cvmx-ipd.h

272

cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);

arch/mips/include/asm/octeon/cvmx-ipd.h

282

cvmx_read_csr

arch/mips/include/asm/octeon/cvmx-ipd.h

300

cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);

arch/mips/include/asm/octeon/cvmx-ipd.h

310

cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);

arch/mips/include/asm/octeon/cvmx-ipd.h

324

ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);

arch/mips/include/asm/octeon/cvmx-ipd.h

332

pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);

arch/mips/include/asm/octeon/cvmx-pip.h

389

stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

390

stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

391

stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

392

stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

393

stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

394

stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

395

stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

396

stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

397

stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

398

stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

400

cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

402

cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

404

cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));

arch/mips/include/asm/octeon/cvmx-pip.h

517

pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));

arch/mips/include/asm/octeon/cvmx-pko.h

587

pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);

arch/mips/include/asm/octeon/cvmx-pko.h

594

pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);

arch/mips/include/asm/octeon/cvmx-pko.h

605

debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);

arch/mips/include/asm/octeon/cvmx-pko.h

611

debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);

arch/mips/include/asm/octeon/cvmx-pow.h

1271

load_resp.u64 = cvmx_read_csr(load_addr.u64);

arch/mips/include/asm/octeon/cvmx-pow.h

1298

load_resp.u64 = cvmx_read_csr(load_addr.u64);

arch/mips/include/asm/octeon/cvmx-pow.h

1366

result.u64 = cvmx_read_csr(ptr.u64);

arch/mips/include/asm/octeon/cvmx-pow.h

1419

result.u64 = cvmx_read_csr(ptr.u64);

arch/mips/include/asm/octeon/cvmx-pow.h

1855

grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));

arch/mips/include/asm/octeon/cvmx-pow.h

1880

grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));

arch/mips/include/asm/octeon/cvmx-spi.h

79

uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));

arch/mips/include/asm/octeon/cvmx.h

299

return cvmx_read_csr((__force uint64_t) csr_addr);

arch/mips/include/asm/octeon/cvmx.h

386

return cvmx_read_csr(node_addr);

arch/mips/include/asm/octeon/cvmx.h

465

c.u64 = cvmx_read_csr(address); \

arch/mips/include/asm/octeon/cvmx.h

491

ciu_fuse = cvmx_read_csr(ciu_fuse_reg);

arch/mips/include/asm/octeon/octeon-feature.h

126

fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);

arch/mips/include/asm/octeon/octeon-model.h

314

static inline uint64_t cvmx_read_csr(uint64_t csr_addr);

arch/mips/pci/msi-octeon.c

252

en = cvmx_read_csr(mis_ena_reg[irq_index]);

arch/mips/pci/msi-octeon.c

255

cvmx_read_csr(mis_ena_reg[irq_index]);

arch/mips/pci/msi-octeon.c

268

en = cvmx_read_csr(mis_ena_reg[irq_index]);

arch/mips/pci/msi-octeon.c

271

cvmx_read_csr(mis_ena_reg[irq_index]);

arch/mips/pci/msi-octeon.c

328

u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \

arch/mips/pci/pci-octeon.c

370

cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pci-octeon.c

382

cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pci-octeon.c

417

cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);

arch/mips/pci/pci-octeon.c

420

cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);

arch/mips/pci/pcie-octeon.c

1036

cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);

arch/mips/pci/pcie-octeon.c

1038

dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);

arch/mips/pci/pcie-octeon.c

1042

dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);

arch/mips/pci/pcie-octeon.c

1051

cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);

arch/mips/pci/pcie-octeon.c

1052

dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);

arch/mips/pci/pcie-octeon.c

1103

pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

1179

qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));

arch/mips/pci/pcie-octeon.c

1209

sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));

arch/mips/pci/pcie-octeon.c

1237

mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));

arch/mips/pci/pcie-octeon.c

1247

ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);

arch/mips/pci/pcie-octeon.c

1254

ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);

arch/mips/pci/pcie-octeon.c

1263

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);

arch/mips/pci/pcie-octeon.c

1265

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pcie-octeon.c

1282

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);

arch/mips/pci/pcie-octeon.c

1286

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pcie-octeon.c

1305

pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

1308

pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

1341

sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);

arch/mips/pci/pcie-octeon.c

1398

pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));

arch/mips/pci/pcie-octeon.c

1404

sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));

arch/mips/pci/pcie-octeon.c

1430

pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

1512

pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));

arch/mips/pci/pcie-octeon.c

1523

pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));

arch/mips/pci/pcie-octeon.c

1533

pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));

arch/mips/pci/pcie-octeon.c

179

pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));

arch/mips/pci/pcie-octeon.c

186

pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));

arch/mips/pci/pcie-octeon.c

1912

npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);

arch/mips/pci/pcie-octeon.c

1917

mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));

arch/mips/pci/pcie-octeon.c

1927

sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));

arch/mips/pci/pcie-octeon.c

1985

dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);

arch/mips/pci/pcie-octeon.c

1991

mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));

arch/mips/pci/pcie-octeon.c

2000

sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));

arch/mips/pci/pcie-octeon.c

2074

sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));

arch/mips/pci/pcie-octeon.c

2081

sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));

arch/mips/pci/pcie-octeon.c

442

npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);

arch/mips/pci/pcie-octeon.c

462

prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));

arch/mips/pci/pcie-octeon.c

469

sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));

arch/mips/pci/pcie-octeon.c

600

pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

628

pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

651

cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));

arch/mips/pci/pcie-octeon.c

718

npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);

arch/mips/pci/pcie-octeon.c

729

npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);

arch/mips/pci/pcie-octeon.c

763

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pcie-octeon.c

774

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);

arch/mips/pci/pcie-octeon.c

780

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);

arch/mips/pci/pcie-octeon.c

783

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pcie-octeon.c

794

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);

arch/mips/pci/pcie-octeon.c

796

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pcie-octeon.c

813

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);

arch/mips/pci/pcie-octeon.c

817

ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);

arch/mips/pci/pcie-octeon.c

836

pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

854

pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

865

pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));

arch/mips/pci/pcie-octeon.c

873

pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));

arch/mips/pci/pcie-octeon.c

889

npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);

arch/mips/pci/pcie-octeon.c

972

npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);

arch/mips/pci/pcie-octeon.c

983

npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);

drivers/ata/pata_octeon_cf.c

105

reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));

drivers/ata/pata_octeon_cf.c

175

reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));

drivers/ata/pata_octeon_cf.c

246

pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);

drivers/ata/pata_octeon_cf.c

604

dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);

drivers/ata/pata_octeon_cf.c

658

dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);

drivers/ata/pata_octeon_cf.c

659

dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);

drivers/edac/octeon_edac-l2c.c

103

err_ttgx.u64 = cvmx_read_csr(CVMX_L2C_ERR_TTGX(tad));

drivers/edac/octeon_edac-l2c.c

157

l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);

drivers/edac/octeon_edac-l2c.c

162

l2d_err.u64 = cvmx_read_csr(CVMX_L2D_ERR);

drivers/edac/octeon_edac-l2c.c

29

l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);

drivers/edac/octeon_edac-l2c.c

44

l2d_err.u64 = cvmx_read_csr(CVMX_L2D_ERR);

drivers/edac/octeon_edac-l2c.c

68

err_tdtx.u64 = cvmx_read_csr(CVMX_L2C_ERR_TDTX(tad));

drivers/edac/octeon_edac-lmc.c

240

cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));

drivers/edac/octeon_edac-lmc.c

263

cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));

drivers/edac/octeon_edac-lmc.c

272

config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));

drivers/edac/octeon_edac-lmc.c

295

en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));

drivers/edac/octeon_edac-lmc.c

44

cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx));

drivers/edac/octeon_edac-lmc.c

47

fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));

drivers/edac/octeon_edac-lmc.c

79

int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));

drivers/edac/octeon_edac-lmc.c

91

fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));

drivers/gpio/gpio-octeon.c

79

u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1008

mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1015

mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1031

drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1088

agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1099

agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1106

cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1114

agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1119

agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1126

cvmx_read_csr(p->agl_prt_ctl);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

1153

cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR));

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

163

mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

175

mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

261

mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

265

mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

300

ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port));

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

311

mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

332

drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

333

bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

353

s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

354

s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

482

mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

490

mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

526

mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

530

cvmx_read_csr(p->mix + MIX_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

533

mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

538

agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

608

agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

675

mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

679

cvmx_read_csr(p->mix + MIX_ISR);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

705

ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

719

u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

749

rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

770

rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

803

prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

812

prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

826

prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

839

prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

884

prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

890

prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);

drivers/net/ethernet/cavium/octeon/octeon_mgmt.c

891

agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK);

drivers/net/mdio/mdio-cavium.h

108

return cvmx_read_csr((u64 __force)addr);

drivers/staging/octeon/ethernet-mdio.c

111

gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

drivers/staging/octeon/ethernet-rgmii.c

31

gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index,

drivers/staging/octeon/ethernet-rgmii.c

38

ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);

drivers/staging/octeon/ethernet-rgmii.c

47

gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index,

drivers/staging/octeon/ethernet-rgmii.c

76

gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG

drivers/staging/octeon/ethernet-rx.c

202

old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid));

drivers/staging/octeon/ethernet-rx.c

205

cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */

drivers/staging/octeon/ethernet-rx.c

207

old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));

drivers/staging/octeon/ethernet-rx.c

391

cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */

drivers/staging/octeon/ethernet-rx.c

96

cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));

drivers/staging/octeon/ethernet-spi.c

112

rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);

drivers/staging/octeon/ethernet-spi.c

127

spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));

drivers/staging/octeon/ethernet-spi.c

140

stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));

drivers/staging/octeon/ethernet-spi.c

85

spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));

drivers/staging/octeon/ethernet-spi.c

88

spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));

drivers/staging/octeon/ethernet-spi.c

92

stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));

drivers/staging/octeon/ethernet-spi.c

95

stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));

drivers/staging/octeon/ethernet-tx.c

235

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

drivers/staging/octeon/ethernet.c

157

ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);

drivers/staging/octeon/ethernet.c

325

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

drivers/staging/octeon/ethernet.c

361

cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

drivers/staging/octeon/ethernet.c

467

gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));

drivers/staging/octeon/ethernet.c

716

cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));

drivers/usb/dwc3/dwc3-octeon.c

216

gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));

drivers/usb/dwc3/dwc3-octeon.c

221

gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));

drivers/usb/dwc3/dwc3-octeon.c

226

gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));

drivers/watchdog/octeon-wdt-main.c

254

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);

drivers/watchdog/octeon-wdt-main.c

256

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);

drivers/watchdog/octeon-wdt-main.c

259

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);

drivers/watchdog/octeon-wdt-main.c

261

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);

drivers/watchdog/octeon-wdt-main.c

264

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);

drivers/watchdog/octeon-wdt-main.c

268

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);

drivers/watchdog/octeon-wdt-main.c

270

octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);