cv1800_clk_regfield_get
clockdiv = cv1800_clk_regfield_get(reg, div);
return cv1800_clk_regfield_get(reg, &mux->mux);
return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)];
factor *= cv1800_clk_regfield_get(regval, &aclk->m);
rate *= cv1800_clk_regfield_get(regval, &aclk->n);