ctrl_regs
const struct msa_control_regs ctrl_regs = {
return membuf_write(&to, &ctrl_regs, sizeof(ctrl_regs));
struct msa_control_regs ctrl_regs;
err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl_regs,
wr_size, wr_size + sizeof(ctrl_regs));
target->thread.fpu.fcr31 = ctrl_regs.fcsr & ~FPU_CSR_ALL_X;
target->thread.fpu.msacsr = ctrl_regs.msacsr & ~MSA_CSR_CAUSEF;
uint64_t *counter_regs, *ctrl_regs;
ctrl_regs = field_offset(ctxt, ctrls);
reg = &ctrl_regs[i];
u8 ctrl_regs[PAC1934_CTRL_REG_LEN];
(u8 *)info->chip_reg_data.ctrl_regs);
samp_rate = samp_rate_map_tbl[((reg_data->ctrl_regs[PAC1934_CTRL_LAT_REG_OFF]) >> 6)];
ctrl_regs_tmp = reg_data->ctrl_regs[PAC1934_CHANNEL_DIS_LAT_REG_OFF];
u8 ctrl_regs[REGS_END];
.ctrl_regs = {
.ctrl_regs = {
.ctrl_regs = {
.ctrl_regs = {
.ctrl_regs = {
.ctrl_regs = {
data->def->ctrl_regs[CNTL], regval);
client, data->def->ctrl_regs[ASA_BASE],
ret = i2c_smbus_read_byte_data(client, data->def->ctrl_regs[ST1]);
data->def->ctrl_regs[ST1]);
return !data->def->ctrl_regs[ST1_DRDY];
ret = i2c_smbus_read_byte_data(client, data->def->ctrl_regs[ST2]);
f30->ctrl_regs, f30->ctrl_regs_size);
u8 *ctrl_reg = f30->ctrl_regs;
f30->ctrl_regs ?: RMI_F30_CTRL_REGS_MAX_SIZE;
u8 ctrl_regs[RMI_F30_CTRL_REGS_MAX_SIZE];
f30->ctrl_regs, f30->ctrl_regs_size);
void __iomem *ctrl_regs;
rpm->ctrl_regs = rpm->status_regs + 0x400;
#define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
priv->ctrl_regs = devm_platform_ioremap_resource_byname(pdev, "ctrl");
if (IS_ERR(priv->ctrl_regs)) {
return PTR_ERR(priv->ctrl_regs);
void __iomem *ctrl_regs;
writel(val, priv->ctrl_regs + offset);
return readl(priv->ctrl_regs + offset);
readl_poll_timeout((priv)->ctrl_regs + (addr), (val), (cond), \
const struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
ctrl_regs->addr);
ath10k_ce_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
(ctrl1_addr & ~(ctrl_regs->dmax->mask)) |
ath10k_set_ring_byte(n, ctrl_regs->dmax));
const struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
ctrl_regs->addr);
ath10k_ce_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
(ctrl1_addr & ~(ctrl_regs->src_ring->mask)) |
ath10k_set_ring_byte(n, ctrl_regs->src_ring));
const struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
ctrl_regs->addr);
ath10k_ce_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
(ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) |
ath10k_set_ring_byte(n, ctrl_regs->dst_ring));
if (!(ptp_qoriq->read(®s->ctrl_regs->tmr_stat) & valid))
} while (ptp_qoriq->read(®s->ctrl_regs->tmr_stat) & valid);
val = ptp_qoriq->read(®s->ctrl_regs->tmr_tevent);
mask = ptp_qoriq->read(®s->ctrl_regs->tmr_temask);
ptp_qoriq->write(®s->ctrl_regs->tmr_tevent, ack);
ptp_qoriq->write(®s->ctrl_regs->tmr_add, tmr_add);
lo = ptp_qoriq->read(®s->ctrl_regs->tmr_cnt_l);
mask = ptp_qoriq->read(®s->ctrl_regs->tmr_temask);
ptp_qoriq->write(®s->ctrl_regs->tmr_tevent, bit);
hi = ptp_qoriq->read(®s->ctrl_regs->tmr_cnt_h);
ptp_qoriq->write(®s->ctrl_regs->tmr_temask, mask);
ptp_qoriq->write(®s->ctrl_regs->tmr_cnt_l, lo);
tmr_ctrl = ptp_qoriq->read(®s->ctrl_regs->tmr_ctrl);
ptp_qoriq->write(®s->ctrl_regs->tmr_cnt_h, hi);
ptp_qoriq->write(®s->ctrl_regs->tmr_ctrl, tmr_ctrl);
ptp_qoriq->regs.ctrl_regs = base + ETSEC_CTRL_REGS_OFFSET;
ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
lo = ptp_qoriq->read(®s->ctrl_regs->tmroff_l);
ptp_qoriq->write(®s->ctrl_regs->tmr_ctrl, tmr_ctrl);
ptp_qoriq->write(®s->ctrl_regs->tmr_add, ptp_qoriq->tmr_add);
ptp_qoriq->write(®s->ctrl_regs->tmr_prsc, ptp_qoriq->tmr_prsc);
hi = ptp_qoriq->read(®s->ctrl_regs->tmroff_h);
ptp_qoriq->write(®s->ctrl_regs->tmr_ctrl,
ptp_qoriq->write(®s->ctrl_regs->tmr_temask, 0);
ptp_qoriq->write(®s->ctrl_regs->tmr_ctrl, 0);
ptp_qoriq->write(®s->ctrl_regs->tmroff_l, lo);
ptp_qoriq->write(®s->ctrl_regs->tmroff_h, hi);
static void snet_write_ctrl(struct snet_ctrl_regs __iomem *ctrl_regs, u32 val)
iowrite32(val, &ctrl_regs->ctrl);
static void snet_write_op(struct snet_ctrl_regs __iomem *ctrl_regs, u32 val)
iowrite32(val, &ctrl_regs->op);
static int snet_wait_for_dpu_completion(struct snet_ctrl_regs __iomem *ctrl_regs)
return snet_wait_for_empty_op(ctrl_regs);
static u32 snet_read32_word(struct snet_ctrl_regs __iomem *ctrl_regs, u16 word_idx)
return ioread32(&ctrl_regs->data[word_idx]);
static u32 snet_read_ctrl(struct snet_ctrl_regs __iomem *ctrl_regs)
return ioread32(&ctrl_regs->ctrl);
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
return (struct lcd_regs __force *)(ctrl_regs(path) + 0xc0);
return (struct lcd_regs __force *)ctrl_regs(path);
return (struct lcd_regs __force *)(ctrl_regs(path) + 0x200);
struct ctrl_regs __iomem *ctrl_regs;