ctrl_dl
if (port->ctrl_dl.CTS) {
const struct ctrl_dl *ctrl_dl = &port->ctrl_dl;
| (ctrl_dl->DCD ? TIOCM_CAR : 0)
| (ctrl_dl->RI ? TIOCM_RNG : 0)
| (ctrl_dl->DSR ? TIOCM_DSR : 0)
| (ctrl_dl->CTS ? TIOCM_CTS : 0);
struct ctrl_dl ctrl_dl;
memset(&dc->port[i].ctrl_dl, 0, sizeof(struct ctrl_dl));
struct ctrl_dl ctrl_dl;
struct ctrl_dl old_ctrl;
read_mem32((u32 *) &ctrl_dl, dc->port[PORT_CTRL].dl_addr[CH_A], 2);
switch (ctrl_dl.port) {
DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),
*((u16 *)&ctrl_dl));
old_ctrl = dc->port[port].ctrl_dl;
dc->port[port].ctrl_dl = ctrl_dl;
if (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) {
} else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) {
if (*(u16 *)&old_ctrl == *(u16 *)&ctrl_dl) {
if (old_ctrl.CTS != ctrl_dl.CTS)
if (old_ctrl.DSR != ctrl_dl.DSR)
if (old_ctrl.RI != ctrl_dl.RI)
if (old_ctrl.DCD != ctrl_dl.DCD)