csrwr32
csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
csrwr32(SGDMA_CTRLREG_RESET, priv->tx_dma_csr, sgdma_csroffs(control));
csrwr32(0, priv->tx_dma_csr, sgdma_csroffs(control));
csrwr32(SGDMA_CTRLREG_RESET, priv->rx_dma_csr, sgdma_csroffs(control));
csrwr32(0, priv->rx_dma_csr, sgdma_csroffs(control));
csrwr32(0, priv->rx_dma_csr, sgdma_csroffs(control));
csrwr32(0xf, priv->rx_dma_csr, sgdma_csroffs(status));
csrwr32(lower_32_bits(raddr), desc, sgdma_descroffs(raddr));
csrwr32(lower_32_bits(waddr), desc, sgdma_descroffs(waddr));
csrwr32(0, desc, sgdma_descroffs(pad1));
csrwr32(0, desc, sgdma_descroffs(pad2));
csrwr32(lower_32_bits(ndesc_phys), desc, sgdma_descroffs(next));
csrwr32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
csrwr32((priv->rxctrlreg | SGDMA_CTRLREG_START),
csrwr32(0, priv->tx_dma_csr, sgdma_csroffs(control));
csrwr32(0x1f, priv->tx_dma_csr, sgdma_csroffs(status));
csrwr32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
csrwr32((priv->txctrlreg | SGDMA_CTRLREG_START),
csrwr32(ctrl, priv->mac_dev, tse_csroffs(command_config));
csrwr32((mii_id & 0x1f), priv->mac_dev,
csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
csrwr32((mii_id & 0x1f), priv->mac_dev,
csrwr32(value, ioaddr, offs);
csrwr32(value, ioaddr, offs);