csi2_reg_write
csi2_reg_write(csi2, discard_regs[i], 0);
csi2_reg_write(csi2, CSI2_STATUS, status);
csi2_reg_write(csi2, CSI2_CH_LENGTH(channel), size >> 4);
csi2_reg_write(csi2, CSI2_CH_STRIDE(channel), stride >> 4);
csi2_reg_write(csi2, CSI2_CH_ADDR1(channel), addr >> 32);
csi2_reg_write(csi2, CSI2_CH_ADDR0(channel), addr & 0xffffffff);
csi2_reg_write(csi2, CSI2_CH_COMP_CTRL(channel), compression);
csi2_reg_write(csi2, CSI2_CH_CTRL(channel), 0);
csi2_reg_write(csi2, CSI2_CH_DEBUG(channel), 0);
csi2_reg_write(csi2, CSI2_STATUS, CSI2_STATUS_IRQ_CH_MASK(channel));
csi2_reg_write(csi2, CSI2_CH_FRAME_SIZE(channel),
csi2_reg_write(csi2, CSI2_CH_FRAME_SIZE(channel), 0);
csi2_reg_write(csi2, CSI2_CH_CTRL(channel), ctrl);
csi2_reg_write(csi2, CSI2_CH_CTRL(channel), CSI2_CH_CTRL_FORCE);
csi2_reg_write(csi2, CSI2_CH_ADDR0(channel), 0);
csi2_reg_write(csi2, CSI2_CH_ADDR0(channel), 0);
csi2_reg_write(csi2, CSI2_IRQ_MASK,
csi2_reg_write(csi2, CSI2_CTRL, CSI2_CTRL_EOP_IS_EOL);
csi2_reg_write(csi2, CSI2_IRQ_MASK, 0);