drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2452

cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

185

dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

34

const struct dpu_csc_cfg *csc_cfg;

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

160

enum mdp4_pipe pipe, struct csc_cfg *csc)

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

316

struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

494

struct csc_cfg *csc)

drivers/gpu/drm/msm/disp/mdp_format.c

14

static struct csc_cfg csc_convert[CSC_MAX] = {

drivers/gpu/drm/msm/disp/mdp_format.c

653

struct csc_cfg *mdp_get_default_csc_cfg(enum csc_type type)

drivers/gpu/drm/msm/disp/mdp_kms.h

124

struct csc_cfg *mdp_get_default_csc_cfg(enum csc_type);