CCU_PARENT_NAME
CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0);
CCU_PARENT_NAME(osc),
CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST,
CCU_PARENT_NAME(osc),
CCU_PARENT_NAME(vctcxo_3m),
CCU_PARENT_NAME(vctcxo_1m),
CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0);
CCU_PARENT_NAME(vctcxo_24m),
CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
CCU_PARENT_NAME(vctcxo_24m),
CCU_PARENT_NAME(vctcxo_24m),
CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0);
CCU_PARENT_NAME(osc_32k),
CCU_PARENT_NAME(vctcxo_1m),
CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST,
CCU_PARENT_NAME(osc_32k),
CCU_PARENT_NAME(vctcxo_3m),
CCU_PARENT_NAME(vctcxo_1m),
CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
CCU_PARENT_NAME(reserved_clk),
CCU_PARENT_NAME(reserved_clk),
CCU_PARENT_NAME(reserved_clk),
CCU_PARENT_NAME(reserved_clk),
CCU_PARENT_NAME(reserved_clk),
CCU_PARENT_NAME(reserved_clk),
CCU_PARENT_NAME(external_clk),
CCU_PARENT_NAME(external_clk),
CCU_PARENT_NAME(vctcxo_24m),
CCU_PARENT_NAME(external_clk),