cmd_val
uint64_t cmd_val:1;
uint64_t cmd_val:1;
uint64_t cmd_val:1;
uint64_t cmd_val:1;
u32 data = cmd_val(s, index + 1);
(cmd_val(s, i) & GENMASK(22, 2))
(cmd_val(s, i) & GENMASK(22, 18))
(cmd_val(s, i) & GENMASK(31, 2))
(cmd_val(s, i) & GENMASK(15, 0))
if (cmd_val(s, 0) & (1 << 22)) {
if (cmd_val(s, 0) & (1 << 22)) {
post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
gma = cmd_val(s, 2) & GENMASK(31, 3);
if (cmd_val(s, 1) & (1 << 21))
val = cmd_val(s, 1) & (~(1 << 21));
if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
dword0 = cmd_val(s, 0);
dword1 = cmd_val(s, 1);
dword2 = cmd_val(s, 2);
u32 dword0 = cmd_val(s, 0);
u32 dword1 = cmd_val(s, 1);
u32 dword2 = cmd_val(s, 2);
u32 cmd = cmd_val(s, 0);
gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
pr_err("\n%08x ", cmd_val(s, i));
pr_err("%08x ", cmd_val(s, i));
int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
if (!(cmd_val(s, 0) & (1 << 22)))
gma = cmd_val(s, 2) & GENMASK(31, 2);
gma_low = cmd_val(s, 1) & GENMASK(31, 2);
gma_high = cmd_val(s, 2) & GENMASK(15, 0);
core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
if (!(cmd_val(s, 0) & (1 << 22)))
if (cmd_val(s, 0) & BIT(18))
gma = cmd_val(s, 1) & GENMASK(31, 2);
gma_high = cmd_val(s, 2) & GENMASK(15, 0);
if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
gma = cmd_val(s, 1) & GENMASK(31, 3);
gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
if (cmd_val(s, 0) & (1 << 21))
val = cmd_val(s, 0) & (~(1 << 21));
if ((cmd_val(s, 0) & (1 << 8)))
(BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
if (cmd_val(s, 0) & BIT(8) &&
cmd = cmd_val(s, 0);
second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
cmd = cmd_val(s, 0);
FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
cmd_val(s, 2), cmd_val(s, 3));
print_opcode(cmd_val(s, 0), s->engine);
gvt_dbg_cmd("%08x ", cmd_val(s, i));
return get_cmd_length(s->info, cmd_val(s, 0));
pdps[0] = (u64)cmd_val(s, 2) << 32;
pdps[0] |= cmd_val(s, 4);
*vreg = cmd_val(s, index + 1);
cmdval = cmd_val(s, index + 1);
u8 cmd_val = inb_p(ABIT_UGURU_BASE + ABIT_UGURU_CMD);
((cmd_val == 0x00) || (cmd_val == 0xAC)))
"0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val);
u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD);
((cmd_val == 0xAC) || (cmd_val == 0x05) ||
(cmd_val == 0x55)))
"0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val);
u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
cmd_val |= SDXC_SEND_INIT_SEQUENCE;
cmd_val |= SDXC_RESP_EXPIRE;
cmd_val |= SDXC_LONG_RESPONSE;
cmd_val |= SDXC_CHECK_RESPONSE_CRC;
cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
cmd_val |= SDXC_SEND_AUTO_STOP;
cmd_val |= SDXC_WRITE;
cmd_val & 0x3f, cmd_val, cmd->arg, imask,
mmc_writel(host, REG_CMDR, cmd_val);
u32 arg, cmd_val, ri;
cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
cmd_val |= SD_IO_RW_DIRECT;
cmd_val |= MMC_STOP_TRANSMISSION;
mmc_writel(host, REG_CMDR, cmd_val);
u16 hash, u16 cmd_mask, u16 cmd_val)
VSC73XX_MACACCESS, cmd_mask, cmd_val);
u32 cmd_val, tmr_idx;
cmd_val = GLTSYN_CMD_INIT_TIME;
cmd_val = GLTSYN_CMD_INIT_INCVAL;
cmd_val = GLTSYN_CMD_ADJ_TIME;
cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
cmd_val = GLTSYN_CMD_READ_TIME;
cmd_val = 0;
return tmr_idx << SEL_CPK_SRC | cmd_val;
u32 cmd_val, tmr_idx;
cmd_val = PHY_CMD_INIT_TIME;
cmd_val = PHY_CMD_INIT_INCVAL;
cmd_val = PHY_CMD_ADJ_TIME;
cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
cmd_val = PHY_CMD_READ_TIME;
cmd_val = 0;
cmd_val = 0;
return tmr_idx << SEL_PHY_SRC | cmd_val;
u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd);
wr32(hw, GLTSYN_CMD, cmd_val);
u32 cmd_val = 0, val = 0;
cmd_val = WX_SPI_CMD_CMD(cmd) |
wr32(wx, WX_SPI_CMD, cmd_val);