cmd_reg
unsigned char cmd_reg;
intersil_clock->cmd_reg=(INTERSIL_RUN|INTERSIL_INT_DISABLE|INTERSIL_24H_MODE);
intersil_clock->cmd_reg=(INTERSIL_RUN|INTERSIL_INT_ENABLE|INTERSIL_24H_MODE);
intersil_clock->cmd_reg = STOP_VAL;
intersil_clock->cmd_reg = START_VAL;
int register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg);
cmd_reg = FIELD_PREP(PSP_CMDRESP_CMD, msg);
iowrite32(cmd_reg, cmd);
cmd_reg = ioread32(cmd);
if (FIELD_GET(PSP_CMDRESP_STS, cmd_reg))
req->header.status = FIELD_GET(PSP_CMDRESP_STS, cmd_reg);
u32 cmd_reg;
u64 cmd_reg, status_reg;
cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK,
cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK,
writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET);
cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET);
out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg);
void __iomem *cmd_reg;
cmd_reg = IS_CHAN_CMD(gpi_cmd) ? gchan->ch_cmd_reg : gpii->ev_cmd_reg;
gpi_write_reg(gpii, cmd_reg, cmd);
cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
memcpy(write_buf, &qcdev->dev_desc.cmd_reg, HIDI2C_REG_LEN);
u32 cmd_reg = 0;
cmd_reg |= MMCCMD_BSYEXP;
cmd_reg |= MMCCMD_RSPFMT_R1456;
cmd_reg |= MMCCMD_RSPFMT_R2;
cmd_reg |= MMCCMD_RSPFMT_R3;
cmd_reg |= MMCCMD_RSPFMT_NONE;
cmd_reg |= cmd->opcode;
cmd_reg |= MMCCMD_DMATRIG;
cmd_reg |= MMCCMD_DMATRIG;
cmd_reg |= MMCCMD_WDATX;
cmd_reg |= MMCCMD_DTRW;
cmd_reg |= MMCCMD_PPLEN;
writel(cmd_reg, host->base + DAVINCI_MMCCMD);
int cmd_reg;
cmd_reg = FIELD_PREP(SDHCI_UHS2_CMD_PACK_LEN_MASK, cmd->uhs2_cmd->packet_len);
cmd_reg |= SDHCI_UHS2_CMD_DATA;
cmd_reg |= SDHCI_UHS2_CMD_CMD12;
cmd_reg |= SDHCI_UHS2_CMD_TRNS_ABORT;
cmd_reg |= SDHCI_UHS2_CMD_DORMANT;
DBG("0x%x is set to UHS2 CMD register.\n", cmd_reg);
sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD);
u32 cmd_reg;
writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
.cmd_reg =
.cmd_reg =
nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz);
nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode);
nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode);
nfc_op->cmd_reg |= CMD_NADDRS(naddrs);
op->cmd_reg = LOONGSON_NAND_CMD_STATUS;
op->cmd_reg = LOONGSON_NAND_CMD_RESET;
op->cmd_reg = LOONGSON_NAND_CMD_READID;
op->cmd_reg = LOONGSON_NAND_CMD_ERASE;
op->cmd_reg = LOONGSON_NAND_CMD_WRITE;
op->cmd_reg = LOONGSON_NAND_CMD_READ;
op->cmd_reg = LOONGSON_NAND_CMD_READ;
op->cmd_reg |= LOONGSON_NAND_CMD_OP_MAIN;
op->cmd_reg |= LOONGSON_NAND_CMD_OP_SPARE;
writel(op->cmd_reg, host->reg_base + LOONGSON_NAND_CMD);
unsigned int cmd_reg;
q_op->cmd_reg = cpu_to_le32(ret);
nandc->regs->cmd = q_op.cmd_reg;
nandc->regs->cmd = q_op.cmd_reg;
} else if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE)) {
q_op.cmd_reg |= cpu_to_le32(PAGE_ACC | LAST_PAGE);
} else if (q_op.cmd_reg != cpu_to_le32(OP_RESET_DEVICE)) {
nandc->regs->cmd = q_op.cmd_reg;
if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE))
q_op.cmd_reg |= cpu_to_le32(PAGE_ACC | LAST_PAGE);
nandc->regs->cmd = q_op.cmd_reg;
__le32 cmd_reg;
int __init register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg)
LCD_CMD_REG = (cmd_reg == LED_CMD_REG_NONE) ? 0 : cmd_reg;
static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
AscSetChipEEPCmd(iop_base, cmd_reg);
if (read_back == cmd_reg)
uchar cmd_reg;
cmd_reg = addr | ASC_EEP_CMD_READ;
AscWriteEEPCmdReg(iop_base, cmd_reg);
u16 cmd_reg;
err = pci_read_config_word(asd_ha->pcidev, PCI_COMMAND, &cmd_reg);
if (cmd_reg & PCI_COMMAND_MEMORY) {
} else if (cmd_reg & PCI_COMMAND_IO) {
u16 cmd_reg;
rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce);
ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN);
ret = regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, val,
ret = regmap_write(r, d->cmd_reg + RC_REG_CFG_UPDATE, 0);
return regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE,
.cmd_reg = 0x0,
u8 cmd_reg;
ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN);
return regmap_read_poll_timeout(r, d->cmd_reg, val, !(val & RC_UPDATE_EN),
u32 portsc, cmd_reg;
cmd_reg = readl(&xhci->op_regs->command);
if (!(cmd_reg & CMD_RUN)) {
__le16 cmd_reg;
union idxd_command_reg cmd_reg = { .cmd = cmd };
writel(cmd_reg.bits, bar0 + IDXD_CMD_OFFSET);