drivers/crypto/cavium/cpt/cptpf_main.c

100

cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);

drivers/crypto/cavium/cpt/cptpf_main.c

106

cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);

drivers/crypto/cavium/cpt/cptpf_main.c

119

cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);

drivers/crypto/cavium/cpt/cptpf_main.c

152

cpt_write_csr64(cpt->reg_base,

drivers/crypto/cavium/cpt/cptpf_main.c

351

cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1);

drivers/crypto/cavium/cpt/cptpf_main.c

39

cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),

drivers/crypto/cavium/cpt/cptpf_main.c

390

cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0);

drivers/crypto/cavium/cpt/cptpf_main.c

405

cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0);

drivers/crypto/cavium/cpt/cptpf_main.c

428

cpt_write_csr64(cpt->reg_base,

drivers/crypto/cavium/cpt/cptpf_main.c

55

cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),

drivers/crypto/cavium/cpt/cptpf_main.c

72

cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),

drivers/crypto/cavium/cpt/cptpf_main.c

86

cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),

drivers/crypto/cavium/cpt/cptpf_main.c

94

cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);

drivers/crypto/cavium/cpt/cptpf_mbox.c

12

cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1),

drivers/crypto/cavium/cpt/cptpf_mbox.c

14

cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg);

drivers/crypto/cavium/cpt/cptpf_mbox.c

31

cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf));

drivers/crypto/cavium/cpt/cptpf_mbox.c

44

cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u);

drivers/crypto/cavium/cpt/cptpf_mbox.c

56

cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u);

drivers/crypto/cavium/cpt/cptpf_mbox.c

79

cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u);

drivers/crypto/cavium/cpt/cptvf_main.c

369

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0), vqx_ctl.u);

drivers/crypto/cavium/cpt/cptvf_main.c

379

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

389

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0), vqx_inprg.u);

drivers/crypto/cavium/cpt/cptvf_main.c

399

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

410

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

422

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

434

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

446

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ENA_W1S(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

458

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

470

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

482

cpt_write_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

494

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

506

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

582

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ACK(0, 0),

drivers/crypto/cavium/cpt/cptvf_main.c

636

cpt_write_csr64(cptvf->reg_base, CPTX_VQX_SADDR(0, 0), vqx_saddr.u);

drivers/crypto/cavium/cpt/cptvf_mbox.c

11

cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0),

drivers/crypto/cavium/cpt/cptvf_mbox.c

13

cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1),