drivers/crypto/cavium/cpt/cptpf_main.c

358

pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0));

drivers/crypto/cavium/cpt/cptpf_main.c

367

bist_sts.u = cpt_read_csr64(cpt->reg_base,

drivers/crypto/cavium/cpt/cptpf_main.c

377

bist_sts.u = cpt_read_csr64(cpt->reg_base,

drivers/crypto/cavium/cpt/cptpf_main.c

38

grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));

drivers/crypto/cavium/cpt/cptpf_main.c

394

grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));

drivers/crypto/cavium/cpt/cptpf_main.c

397

grp = cpt_read_csr64(cpt->reg_base,

drivers/crypto/cavium/cpt/cptpf_main.c

42

grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));

drivers/crypto/cavium/cpt/cptpf_main.c

45

grp = cpt_read_csr64(cpt->reg_base,

drivers/crypto/cavium/cpt/cptpf_main.c

54

pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));

drivers/crypto/cavium/cpt/cptpf_main.c

71

pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));

drivers/crypto/cavium/cpt/cptpf_main.c

85

pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));

drivers/crypto/cavium/cpt/cptpf_mbox.c

151

intr = cpt_read_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0));

drivers/crypto/cavium/cpt/cptpf_mbox.c

41

pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf));

drivers/crypto/cavium/cpt/cptpf_mbox.c

54

pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf));

drivers/crypto/cavium/cpt/cptpf_mbox.c

77

pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q));

drivers/crypto/cavium/cpt/cptpf_mbox.c

96

mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0));

drivers/crypto/cavium/cpt/cptpf_mbox.c

97

mbx.data = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1));

drivers/crypto/cavium/cpt/cptvf_main.c

367

vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0));

drivers/crypto/cavium/cpt/cptvf_main.c

376

vqx_dbell.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

387

vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0));

drivers/crypto/cavium/cpt/cptvf_main.c

396

vqx_dwait.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

407

vqx_dwait.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

418

vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

430

vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

442

vqx_done_ena.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

454

vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

466

vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

478

vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

490

vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

502

vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_main.c

512

return cpt_read_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0));

drivers/crypto/cavium/cpt/cptvf_main.c

570

vqx_done.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_DONE(0, 0));

drivers/crypto/cavium/cpt/cptvf_main.c

579

vqx_dack_cnt.u = cpt_read_csr64(cptvf->reg_base,

drivers/crypto/cavium/cpt/cptvf_mbox.c

26

mbx.msg = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0));

drivers/crypto/cavium/cpt/cptvf_mbox.c

27

mbx.data = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1));