cprman_read
div = cprman_read(cprman, data->div_reg);
while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
cprman_read(cprman, data->ctl_reg) |
ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
u32 src = cprman_read(cprman, data->ctl_reg);
if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
while (cprman_read(cprman, CM_OSCCOUNT)) {
while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
count = cprman_read(cprman, CM_TCNTCNT);
return cprman_read(cprman, data->a2w_ctrl_reg) &
u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
cprman_read(cprman, data->a2w_ctrl_reg) |
cprman_read(cprman, data->a2w_ctrl_reg) &
cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
cprman_read(cprman, data->a2w_ctrl_reg) |
ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
cprman_read(cprman, A2W_XOSC_CTRL) |
a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
(cprman_read(cprman, data->cm_reg) &
cprman_read(cprman, data->a2w_reg) |
cprman_read(cprman, data->a2w_reg) &
cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
cm = cprman_read(cprman, data->cm_reg);
return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;