CCI_REG24
#define REG_HALF_PIX_CLK CCI_REG24(0xe085)
#define REG_BYTE_CLK CCI_REG24(0xe092)
#define MAX96714_PATGEN_VS_DLY CCI_REG24(0x242)
#define MAX96714_PATGEN_VS_HIGH CCI_REG24(0x245)
#define MAX96714_PATGEN_VS_LOW CCI_REG24(0x248)
#define MAX96714_PATGEN_V2H CCI_REG24(0x24b)
#define MAX96714_PATGEN_V2D CCI_REG24(0x254)
#define MAX96714_PATGEN_CHKB_COLOR_A CCI_REG24(0x25e)
#define MAX96714_PATGEN_CHKB_COLOR_B CCI_REG24(0x261)
#define MAX96717_VTX_VS_DLY CCI_REG24(0x250)
#define MAX96717_VTX_VS_HIGH CCI_REG24(0x253)
#define MAX96717_VTX_VS_LOW CCI_REG24(0x256)
#define MAX96717_VTX_V2H CCI_REG24(0x259)
#define MAX96717_VTX_V2D CCI_REG24(0x262)
#define MAX96717_VTX_CHKB_COLOR_A CCI_REG24(0x26d)
#define MAX96717_VTX_CHKB_COLOR_B CCI_REG24(0x270)
#define OG01A1B_REG_CHIP_ID CCI_REG24(0x300a)
#define OG01A1B_REG_DIG_GAIN CCI_REG24(0x350a)
#define OG0VE1B_REG_CHIP_ID CCI_REG24(0x300a)
#define OG0VE1B_REG_EXPOSURE CCI_REG24(0x3500)
#define OS05B10_REG_CHIP_ID CCI_REG24(0x300a)
#define OS05B10_REG_EXPOSURE CCI_REG24(0x3500)
#define OV01A10_REG_CHIP_ID CCI_REG24(0x300a)
#define OV01A10_REG_DIGITAL_GAIN_B CCI_REG24(0x350a)
#define OV01A10_REG_DIGITAL_GAIN_GB CCI_REG24(0x3510)
#define OV01A10_REG_DIGITAL_GAIN_GR CCI_REG24(0x3513)
#define OV01A10_REG_DIGITAL_GAIN_R CCI_REG24(0x3516)
#define OV02C10_REG_DIGITAL_GAIN CCI_REG24(0x350a)
#define OV2680_REG_EXPOSURE_PK CCI_REG24(0x3500)
#define OV2732_REG_CHIP_ID CCI_REG24(0x300a)
#define OV2732_REG_EXPOSURE CCI_REG24(0x3500)
#define OV4689_REG_EXPOSURE CCI_REG24(0x3500)
#define OV5647_REG_EXPOSURE CCI_REG24(0x3500)
#define OV5693_EXPOSURE_CTRL_REG CCI_REG24(0x3500)
#define OV6211_REG_EXPOSURE CCI_REG24(0x3500)
#define OV64A40_REG_CHIP_ID CCI_REG24(0x300a)
#define OV64A40_REG_MEC_LONG_EXPO CCI_REG24(0x3500)
#define OV9282_REG_EXPOSURE CCI_REG24(0x3500)