drivers/clk/imx/clk-imx95-blk-ctl.c

49

u32 clk_type;

drivers/clk/imx/clk-scu.c

253

msg.data.req.clk = clk->clk_type;

drivers/clk/imx/clk-scu.c

326

msg.clk = clk->clk_type;

drivers/clk/imx/clk-scu.c

33

u8 clk_type;

drivers/clk/imx/clk-scu.c

344

msg.data.req.clk = clk->clk_type;

drivers/clk/imx/clk-scu.c

371

msg.clk = clk->clk_type;

drivers/clk/imx/clk-scu.c

416

clk->clk_type, true, false);

drivers/clk/imx/clk-scu.c

431

clk->clk_type, false, false);

drivers/clk/imx/clk-scu.c

463

u32 rsrc_id, u8 clk_type)

drivers/clk/imx/clk-scu.c

475

clk->clk_type = clk_type;

drivers/clk/imx/clk-scu.c

52

u8 clk_type;

drivers/clk/imx/clk-scu.c

521

if (clk->clk_type == idx)

drivers/clk/imx/clk-scu.c

551

clk->rsrc, clk->clk_type);

drivers/clk/imx/clk-scu.c

566

clk->clk_type);

drivers/clk/imx/clk-scu.c

680

int num_parents, u32 rsrc_id, u8 clk_type)

drivers/clk/imx/clk-scu.c

685

.clk_type = clk_type,

drivers/clk/imx/clk-scu.c

701

name, rsrc_id, clk_type);

drivers/clk/imx/clk-scu.c

917

clk_node->clk_type = gpr_id;

drivers/clk/imx/clk-scu.h

36

int num_parents, u32 rsrc_id, u8 clk_type);

drivers/clk/imx/clk-scu.h

40

u32 rsrc_id, u8 clk_type);

drivers/clk/imx/clk-scu.h

54

u8 clk_type)

drivers/clk/imx/clk-scu.h

56

return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);

drivers/clk/imx/clk-scu.h

60

int num_parents, u32 rsrc_id, u8 clk_type)

drivers/clk/imx/clk-scu.h

62

return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);

drivers/clk/zynqmp/clkc.c

74

enum clk_type type;

drivers/gpu/drm/amd/amdgpu/atombios_crtc.c

526

u32 freq, u8 clk_type, u8 clk_src)

drivers/gpu/drm/amd/amdgpu/atombios_crtc.c

545

args.v2_1.asParam.ucDCEClkType = clk_type;

drivers/gpu/drm/amd/amdgpu/atombios_crtc.h

41

u32 freq, u8 clk_type, u8 clk_src);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

113

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

122

switch (clk_type) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

269

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

278

dc_to_pp_clock_type(clk_type), &pp_clks)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

280

get_default_clock_levels(clk_type, dc_clks);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

284

pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

304

if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

317

} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

333

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

341

dc_to_pp_clock_type(clk_type),

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

346

pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

353

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

361

dc_to_pp_clock_type(clk_type),

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

366

pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

398

pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

101

clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

86

clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1319

static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1325

switch (clk_type) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1523

unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1529

switch (clk_type) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

115

unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

850

unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

856

switch (clk_type) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

73

unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

drivers/gpu/drm/amd/display/dc/dm_services.h

192

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/dc/dm_services.h

197

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/dc/dm_services.h

202

enum dm_pp_clock_type clk_type,

drivers/gpu/drm/amd/display/dc/dm_services_types.h

227

enum dm_pp_clock_type clk_type;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

59

#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

60

(clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

61

(clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

62

(clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

63

(clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

64

(clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

65

(clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

66

(clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

67

(clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

68

(clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \

drivers/gpu/drm/amd/display/dc/dm_services_types.h

69

(clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

386

unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

55

enum amd_pp_clock_type clk_type = clock_req->clock_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

59

switch (clk_type) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4037

enum amd_pp_clock_type clk_type = clock_req->clock_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4042

switch (clk_type) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1578

enum amd_pp_clock_type clk_type = clock_req->clock_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1584

switch (clk_type) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2303

enum amd_pp_clock_type clk_type = clock_req->clock_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2309

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

147

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

150

clk_type = smu_convert_to_smuclk(type);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

151

if (clk_type == SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

156

clk_type,

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

165

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

176

clk_type,

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2623

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2638

ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2640

smu->user_dpm_profile.clk_mask[clk_type] = mask;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2641

smu_set_user_clk_dependencies(smu, clk_type);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2653

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2657

clk_type = SMU_SCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2659

clk_type = SMU_MCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2661

clk_type = SMU_PCIE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2663

clk_type = SMU_SOCCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2665

clk_type = SMU_FCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2667

clk_type = SMU_DCEFCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2669

clk_type = SMU_VCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2671

clk_type = SMU_VCLK1; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2673

clk_type = SMU_DCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2675

clk_type = SMU_DCLK1; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2677

clk_type = SMU_OD_SCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2679

clk_type = SMU_OD_MCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2681

clk_type = SMU_OD_VDDC_CURVE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2683

clk_type = SMU_OD_RANGE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

2688

return smu_force_smuclk_levels(smu, clk_type, mask);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3046

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3050

clk_type = SMU_SCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3052

clk_type = SMU_MCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3054

clk_type = SMU_PCIE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3056

clk_type = SMU_SOCCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3058

clk_type = SMU_FCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3060

clk_type = SMU_DCEFCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3062

clk_type = SMU_VCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3064

clk_type = SMU_VCLK1; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3066

clk_type = SMU_DCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3068

clk_type = SMU_DCLK1; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3070

clk_type = SMU_ISPICLK;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3073

clk_type = SMU_ISPXCLK;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3076

clk_type = SMU_OD_SCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3078

clk_type = SMU_OD_MCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3080

clk_type = SMU_OD_FCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3082

clk_type = SMU_OD_VDDC_CURVE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3084

clk_type = SMU_OD_RANGE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3086

clk_type = SMU_OD_VDDGFX_OFFSET; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3088

clk_type = SMU_OD_CCLK; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3090

clk_type = SMU_OD_FAN_CURVE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3092

clk_type = SMU_OD_ACOUSTIC_LIMIT; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3094

clk_type = SMU_OD_ACOUSTIC_TARGET; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3096

clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3098

clk_type = SMU_OD_FAN_MINIMUM_PWM; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3100

clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3102

clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3104

clk_type = SMU_CLK_COUNT; break;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3107

return clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3113

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3115

clk_type = smu_convert_to_smuclk(type);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3116

if (clk_type == SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3125

return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3438

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3447

clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3450

clk_type = SMU_MCLK;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3453

clk_type = SMU_DCEFCLK;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3456

clk_type = SMU_DISPCLK;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

3463

ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

525

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

527

for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

532

if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

533

smu->user_dpm_profile.clk_mask[clk_type]) {

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

534

ret = smu_force_smuclk_levels(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

535

smu->user_dpm_profile.clk_mask[clk_type]);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

538

"Failed to set clock type = %d\n", clk_type);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

65

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1436

int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1442

int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max,

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1969

int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1972

int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

319

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

874

int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

882

int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

905

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

221

int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

224

int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

228

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

239

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

244

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

248

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v12_0.h

56

int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

193

int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

196

int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

206

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

210

enum smu_clk_type clk_type, uint16_t level,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

275

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

158

int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

161

int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

165

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

176

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

168

int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

171

int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

175

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

186

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

366

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

383

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

400

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

417

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

702

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

713

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

263

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

268

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

294

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

301

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

328

ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

335

ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

542

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

549

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

556

ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1008

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1025

dpm_table->clk_type = SMU_VCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1042

dpm_table->clk_type = SMU_DCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1059

dpm_table->clk_type = SMU_DCEFCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1076

dpm_table->clk_type = SMU_PIXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1093

dpm_table->clk_type = SMU_DISPCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1110

dpm_table->clk_type = SMU_PHYCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1174

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1182

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1214

static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1222

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1248

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1267

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1400

ret = navi10_get_current_clk_freq_by_table(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1412

enum smu_clk_type clk_type, uint32_t mask)

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1421

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1429

ret = navi10_is_support_fine_grained_dpm(smu, clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1438

ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1442

ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1446

ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1550

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1556

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1562

ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1570

ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

974

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

991

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1000

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1017

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1038

dpm_table->clk_type = i ? SMU_VCLK1 : SMU_VCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1060

dpm_table->clk_type = i ? SMU_DCLK1 : SMU_DCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1079

dpm_table->clk_type = SMU_DCEFCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1096

dpm_table->clk_type = SMU_PIXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1113

dpm_table->clk_type = SMU_DISPCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1130

dpm_table->clk_type = SMU_PHYCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1194

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1202

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1244

static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1253

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1271

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1288

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1390

smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1403

enum smu_clk_type clk_type, uint32_t mask)

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1411

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1419

if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1424

ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1428

ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1432

ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2153

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2156

return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

965

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

983

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1639

int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1646

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1647

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1675

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1699

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1707

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1712

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1743

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1753

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1758

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1903

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1913

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1918

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1941

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1945

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1951

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1959

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1968

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

986

enum amd_pp_clock_type clk_type = clock_req->clock_type;

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

993

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1003

ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1008

ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1013

ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1018

ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1083

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1090

if (!vangogh_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1093

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1166

enum smu_clk_type clk_type, uint32_t mask)

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1175

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1177

ret = vangogh_get_dpm_clk_limited(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1181

ret = vangogh_get_dpm_clk_limited(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1198

clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1202

clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1218

clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1223

clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1243

clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1248

clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1276

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1286

clk_type = clks[i];

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1287

ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1292

ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1304

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1307

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1321

clk_type = clk_feature_map[i].clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1323

ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1328

ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

523

static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

528

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

531

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

567

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

583

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

638

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

645

idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

646

ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

670

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

686

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

742

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

749

idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

750

ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

792

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

798

ret = vangogh_emit_legacy_clk_levels(smu, clk_type, buf, offset);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

800

ret = vangogh_emit_clk_levels(smu, clk_type, buf, offset);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

860

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

864

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

892

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

904

if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

905

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

950

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

953

ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

958

ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

963

ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

968

ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

973

ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

995

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

998

ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

195

static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

200

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

203

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

274

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

282

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

283

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

318

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

330

ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

335

ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

346

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

358

ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

363

ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

488

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

502

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

574

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

582

idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

583

ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

686

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

695

clk_type = clks[i];

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

696

ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

701

ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

713

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

716

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

728

clk_type = clk_feature_map[i].clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

730

ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

734

ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

787

enum smu_clk_type clk_type, uint32_t mask)

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

796

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

821

ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

824

ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

836

ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

839

ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

905

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

910

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

175

int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

180

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

183

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1234

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1247

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

342

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

350

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

390

return smu_v13_0_get_dpm_ultimate_freq(smu, clk_type, min, max);

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

405

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

420

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

437

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

452

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

726

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

737

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1440

int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1447

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1448

ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1463

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1496

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1504

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1509

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1743

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1748

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1777

enum smu_clk_type clk_type, uint16_t level,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1786

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1787

return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1791

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1810

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1815

ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1824

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1834

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1839

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1862

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1871

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1879

ret = smu_v13_0_get_fine_grained_status(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1891

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1003

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1201

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1220

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1480

ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1942

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1955

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1982

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2007

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

572

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

587

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

618

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

633

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

648

dpm_table->clk_type = SMU_VCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

663

dpm_table->clk_type = SMU_DCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

678

dpm_table->clk_type = SMU_DCEFCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

859

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

867

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

995

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

394

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

399

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

430

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

436

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

439

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

474

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

479

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

503

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

510

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

529

ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

533

ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

538

idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

539

ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

549

ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

728

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

732

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

757

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

766

if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

767

ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

781

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

802

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

803

ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

812

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

833

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

834

ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

844

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

853

if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

856

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

879

if (clk_type == SMU_VCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

893

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

903

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

908

ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

912

ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

916

ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

928

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

935

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

601

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

606

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

632

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

637

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

661

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

667

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

670

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

705

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

709

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

734

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

743

if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

744

ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

758

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

780

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

781

ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

788

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

810

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

811

ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

822

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

832

if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

835

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

850

if (clk_type == SMU_VCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

868

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

875

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

892

ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

896

ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

901

idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

902

ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

912

ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

942

enum smu_clk_type clk_type, uint32_t mask)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

951

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

954

ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

958

ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

962

ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

977

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

984

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1003

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1039

if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1041

smu, CMN2ASIC_MAPPING_CLK, clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1050

if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1061

if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1074

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1079

ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1135

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1161

smu, dpm_map[j].clk_type, &levels);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1166

dpm_table->clk_type = dpm_map[j].clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1350

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1358

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2057

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2069

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2070

clk_type != SMU_UCLK && clk_type != SMU_FCLK)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2084

if (clk_type == SMU_GFXCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2097

if (clk_type == SMU_UCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2111

if (clk_type == SMU_FCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

253

enum smu_clk_type clk_type;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

990

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1005

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1013

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1211

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1230

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1490

ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1952

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1965

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1992

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2017

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

600

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

615

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

637

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

652

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

667

dpm_table->clk_type = SMU_VCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

682

dpm_table->clk_type = SMU_DCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

697

dpm_table->clk_type = SMU_DCEFCLK;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

869

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

877

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1012

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1017

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1048

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1056

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1074

ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1078

ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1083

idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1084

ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1094

clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1095

ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1124

enum smu_clk_type clk_type, uint32_t mask)

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1133

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1138

ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1142

ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1146

ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1161

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1168

clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1170

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

732

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

737

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

766

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

771

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

795

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

801

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

804

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

839

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

843

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

868

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

877

if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

878

ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

892

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

914

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

915

ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

922

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

944

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

945

ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

956

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

967

if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

970

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

993

if (clk_type == SMU_VCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1031

int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1038

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1039

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1067

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1100

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1108

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1113

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1145

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1155

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1160

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1373

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1383

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1388

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1407

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1412

ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1418

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1428

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1433

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1456

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1465

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1472

ret = smu_v14_0_get_fine_grained_status(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1483

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1006

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1007

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1018

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1023

smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1024

else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1025

smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1031

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1036

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1070

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1075

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1101

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1106

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1130

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1134

smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1135

else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1136

smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1142

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1149

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1170

ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1174

ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1179

idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1180

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1190

ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1219

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1228

if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1231

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1276

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1286

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1293

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1297

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1301

ret = smu_v14_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1313

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1320

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

640

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

646

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

649

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

694

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

700

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

703

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

738

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

743

smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

744

else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

745

smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

751

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

755

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

782

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

791

if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

792

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

830

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

858

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

859

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

866

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

892

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

893

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

904

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

913

if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

914

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

950

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

974

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

975

ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

982

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1032

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1051

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1289

ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1306

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1319

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1346

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1371

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

472

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

487

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

518

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

533

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

548

dpm_table->clk_type = SMU_VCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

563

dpm_table->clk_type = SMU_DCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

578

dpm_table->clk_type = SMU_DCEFCLK;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

747

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

755

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

882

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

890

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1016

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1026

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1031

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1244

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1254

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1259

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1278

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1283

ret = smu_v15_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1289

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1299

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1304

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1327

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1336

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1344

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

1356

clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

903

int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

910

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

911

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

939

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

972

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

980

if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

985

clk_type);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1000

enum smu_clk_type clk_type, char *buf,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1007

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1028

ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1032

ret = smu_v15_0_common_get_dpm_level_count(smu, clk_type, &count);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1037

idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1038

ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1049

ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1079

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1086

if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1089

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1121

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1131

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1138

ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1142

ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1146

ret = smu_v15_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1158

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1165

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

712

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

718

if (!clk_table || clk_type >= SMU_CLK_COUNT)

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

721

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

756

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

760

smu_v15_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

766

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

770

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

797

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

806

if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type)) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

807

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

843

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

867

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

868

ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

875

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

899

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

900

ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

911

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

915

if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

916

smu_v15_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

922

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

927

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

961

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

966

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

990

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

993

if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

994

smu_v15_0_0_get_dpm_level_count(smu, clk_type, count);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1977

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1985

if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1986

clk_type != SMU_UCLK)

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1998

if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

2011

if (clk_type == SMU_UCLK) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

459

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

467

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

762

enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

776

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

820

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

874

dpm_table->clk_type = SMU_GFXCLK;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

895

dpm_table->clk_type = SMU_FCLK;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

926

dpm_table->clk_type = SMU_UCLK;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

942

dpm_table->clk_type = SMU_SOCCLK;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

950

dpm_table->clk_type = SMU_VCLK;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

958

dpm_table->clk_type = SMU_DCLK;

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

775

enum smu_clk_type clk_type)

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

779

switch (clk_type) {

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

166

enum smu_clk_type clk_type);

drivers/input/evdev.c

146

struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]);

drivers/input/evdev.c

177

enum input_clock_type clk_type;

drivers/input/evdev.c

182

clk_type = INPUT_CLK_REAL;

drivers/input/evdev.c

185

clk_type = INPUT_CLK_MONO;

drivers/input/evdev.c

188

clk_type = INPUT_CLK_BOOT;

drivers/input/evdev.c

194

if (client->clk_type != clk_type) {

drivers/input/evdev.c

195

client->clk_type = clk_type;

drivers/input/evdev.c

256

ts = ktime_to_timespec64(ev_time[client->clk_type]);

drivers/input/evdev.c

49

enum input_clock_type clk_type;

drivers/media/dvb-frontends/mxl5xx.c

1382

u32 clk_type = 0;

drivers/media/dvb-frontends/mxl5xx.c

1465

clk_type = 1;

drivers/media/dvb-frontends/mxl5xx.c

1472

clk_type);

drivers/media/dvb-frontends/mxl5xx.c

1474

update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);

drivers/media/platform/qcom/iris/iris_platform_common.h

80

enum platform_clk_type clk_type;

drivers/media/platform/qcom/iris/iris_resources.c

101

static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platform_clk_type clk_type)

drivers/media/platform/qcom/iris/iris_resources.c

110

if (clk_tbl[i].clk_type == clk_type) {

drivers/media/platform/qcom/iris/iris_resources.c

121

int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type)

drivers/media/platform/qcom/iris/iris_resources.c

125

clock = iris_get_clk_by_type(core, clk_type);

drivers/media/platform/qcom/iris/iris_resources.c

132

int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type)

drivers/media/platform/qcom/iris/iris_resources.c

136

clock = iris_get_clk_by_type(core, clk_type);

drivers/media/platform/qcom/iris/iris_resources.h

16

int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type);

drivers/media/platform/qcom/iris/iris_resources.h

17

int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type);

drivers/nfc/s3fwrn5/nci.c

71

fw_cfg.clk_type = 0x01;

drivers/nfc/s3fwrn5/nci.h

44

__u8 clk_type;

drivers/phy/phy-xgene.c

1137

enum clk_type_t clk_type)

drivers/phy/phy-xgene.c

1237

enum clk_type_t clk_type)

drivers/phy/phy-xgene.c

1254

enum clk_type_t clk_type, int ssc_enable)

drivers/phy/phy-xgene.c

1284

xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type);

drivers/phy/phy-xgene.c

1287

xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type);

drivers/phy/phy-xgene.c

1305

if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type))

drivers/phy/phy-xgene.c

1308

xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type);

drivers/phy/phy-xgene.c

1318

enum clk_type_t clk_type,

drivers/phy/phy-xgene.c

1323

dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type);

drivers/phy/phy-xgene.c

1326

rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable);

drivers/phy/phy-xgene.c

535

enum clk_type_t clk_type; /* Input clock selection */

drivers/phy/phy-xgene.c

706

enum clk_type_t clk_type)

drivers/phy/phy-xgene.c

719

if (clk_type == CLK_EXT_DIFF) {

drivers/phy/phy-xgene.c

729

} else if (clk_type == CLK_INT_DIFF) {

drivers/phy/phy-xgene.c

739

} else if (clk_type == CLK_INT_SING) {

drivers/phy/phy-xgene.c

760

enum clk_type_t clk_type)

drivers/phy/phy-xgene.c

806

if (clk_type == CLK_EXT_DIFF)

drivers/video/fbdev/aty/atyfb_base.c

2371

u8 dac_subtype, clk_type;

drivers/video/fbdev/aty/atyfb_base.c

2378

clk_type = CLK_ATI18818_1;

drivers/video/fbdev/aty/atyfb_base.c

2386

clk_type = CLK_IBMRGB514;

drivers/video/fbdev/aty/atyfb_base.c

2407

switch (clk_type) {

sound/soc/codecs/wcd9335.c

324

enum wcd_clock_type clk_type;

sound/soc/codecs/wcd9335.c

4082

if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||

sound/soc/codecs/wcd9335.c

4083

((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {

sound/soc/codecs/wcd9335.c

4085

wcd->clk_type);

sound/soc/codecs/wcd9335.c

4114

wcd->clk_type = WCD_CLK_MCLK;

sound/soc/codecs/wcd9335.c

4130

wcd->clk_type = WCD_CLK_RCO;

sound/soc/codecs/wcd9335.c

4135

wcd->clk_type = WCD_CLK_OFF;