drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1061

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1063

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1065

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1070

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1073

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1075

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

333

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

334

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

335

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

336

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1401

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1404

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

366

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

367

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

368

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

369

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1272

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1277

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1282

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1287

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1292

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1297

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1302

CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

371

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

372

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

373

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

374

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

375

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

376

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

377

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1105

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1109

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1113

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1117

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1121

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1125

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1131

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

409

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

410

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

411

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

412

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

413

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

414

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

415

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1149

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1151

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1153

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1158

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1161

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1163

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1348

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1350

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1355

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1358

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1360

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

359

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

360

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

361

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

362

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

953

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

955

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

960

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

963

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

965

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1163

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1165

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1167

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1172

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1175

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1177

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1365

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1367

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1372

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1375

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

359

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

360

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

361

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

362

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

963

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

965

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

967

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

972

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

975

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

977

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1456

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1460

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1464

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1470

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1482

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

502

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

503

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

504

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

505

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

506

clk_src_regs(3, D)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

194

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

195

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

196

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

197

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

198

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

199

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

200

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2547

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2551

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2555

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2559

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2563

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2567

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2573

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1203

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1207

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1215

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

311

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

312

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

313

clk_src_regs(1, B)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1520

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1524

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1528

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

153

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1532

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1536

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

154

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1544

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

155

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

156

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

157

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

158

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

203

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

204

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

205

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

206

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

207

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

208

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

209

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2560

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2564

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2568

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2572

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2576

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2580

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2588

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1555

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1559

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1563

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1567

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1575

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

204

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

205

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

206

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

207

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

208

clk_src_regs(3, D)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1457

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1461

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1465

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1469

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1473

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1481

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

545

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

546

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

547

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

548

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

549

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

550

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1401

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1405

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1413

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

532

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

533

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

534

clk_src_regs(1, B)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

214

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

215

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

216

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2167

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

217

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2171

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

218

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2186

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

219

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2190

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2196

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2204

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

223

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

224

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

225

clk_src_regs(2, F),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

226

clk_src_regs(3, G),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

227

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2100

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2104

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2108

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2112

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2116

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2124

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

231

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

232

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

233

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

234

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

235

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

236

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2132

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2136

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2140

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2144

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2148

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2156

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

225

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

226

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

227

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

228

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

229

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

230

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2004

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2008

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2012

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2016

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2020

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2028

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

211

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

212

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

213

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

214

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

215

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

216

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

224

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2319

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2491

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2495

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2499

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2503

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2507

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2515

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1814

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1984

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1988

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1992

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1996

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2000

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2008

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

218

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1985

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2135

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2139

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2143

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2147

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2151

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2159

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

231

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1958

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2107

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

211

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2111

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2115

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2119

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2123

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2131

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1958

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2105

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2109

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2113

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2117

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2121

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2129

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

216

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2010

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

203

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2194

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2198

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2202

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2206

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2218

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1974

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2182

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2186

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2190

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2194

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2198

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

220

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2206

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1926

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2142

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2146

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2150

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2158

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

253

static struct dce110_clk_src_regs clk_src_regs[5];