counter_mask
unsigned long counter_mask = 0;
set_bit(leader->attr.config, &counter_mask);
if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask))
if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
cntrs_mask = counter_mask(eax, ebx);
hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);
hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);
pebs_mask = counter_mask(eax, ecx);
pdists_mask = counter_mask(ebx, edx);
u64 val = counter_mask(cspmu) >> 1ULL;
delta = (now - prev) & counter_mask(cspmu);
u64 counter_mask;
if (smmu_pmu->counter_mask & BIT(32))
if (smmu_pmu->counter_mask & BIT(32))
delta &= smmu_pmu->counter_mask;
new = smmu_pmu->counter_mask >> 1;
smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
.counter_mask = OMAP4460_COUNTER_MASK,
.counter_mask = OMAP5430_COUNTER_MASK,
.counter_mask = OMAP5430_COUNTER_MASK,
.counter_mask = OMAP5430_COUNTER_MASK,
RMW_BITS(bgp, i, bgap_counter, counter_mask,
time = (time & tsr->counter_mask) >>
__ffs(tsr->counter_mask);
RMW_BITS(bgp, id, bgap_counter, counter_mask, interval);
RMW_BITS(bgp, i, bgap_counter, counter_mask, 1);
u32 counter_mask;