clk_register_fixed_factor
c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
clk_register_fixed_factor(dev, "nand_clka", "cpu", 0, 1, 8);
clk_register_fixed_factor(dev, "eth_aclk", "cpu", 0, 1, 4);
clk_register_fixed_factor(dev, "dma_aclk", "cpu", 0, 1, 4);
clk_register_fixed_factor(dev, "i2s_hst", "cpu", 0, 1, 8);
clk_register_fixed_factor(dev, i2s_clk_names[i],
clk_register_fixed_factor(dev, i2s_clk_names[i],
clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
clk = clk_register_fixed_factor(NULL, name, input_name,
clk = clk_register_fixed_factor(NULL,
clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk",
oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
prediv_clk = clk_register_fixed_factor(dev, prediv_name,
clk = clk_register_fixed_factor(NULL, clks[i].name,
clk = clk_register_fixed_factor(NULL, clks[i].name,
ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
ap806_clks[4] = clk_register_fixed_factor(NULL, name,
clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
return clk_register_fixed_factor(NULL, name, parent_name,
clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent,
clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
clk_register_fixed_factor(NULL, "os-timer0",
clk = clk_register_fixed_factor(dev, "acpu_aux",
return clk_register_fixed_factor(NULL, name, parent_name, 0,
return clk_register_fixed_factor(NULL, name, parent_name, 0,
return clk_register_fixed_factor(NULL, "plla",
return clk_register_fixed_factor(NULL, "pllb",
return clk_register_fixed_factor(NULL,
return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
return clk_register_fixed_factor(NULL, name, parent_name, 0,
return clk_register_fixed_factor(NULL, core->name,
clk = clk_register_fixed_factor(NULL, d->name,
return clk_register_fixed_factor(NULL, core->name, parent_name,
return clk_register_fixed_factor(NULL, core->name,
return clk_register_fixed_factor(NULL, core->name,
clk = clk_register_fixed_factor(NULL, core->name,
return clk_register_fixed_factor(NULL, name,
clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
clk = clk_register_fixed_factor(NULL, data->name_2x,
clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",
clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",
clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,