drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

157

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

167

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

177

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

201

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

215

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

243

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

318

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

368

struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

401

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

100

int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

117

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

131

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

160

struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

202

struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

241

static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

259

void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

357

struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

33

int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

41

struct clk_mgr_internal *clk_mgr_dce);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

43

void dce_clock_read_ss_info(struct clk_mgr_internal *dccg_dce);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

247

struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

268

struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

31

struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

104

int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

137

int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

167

struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

188

struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

59

struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

32

struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

36

int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

37

int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

116

void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

124

void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

44

static void dce121_clock_patch_xgmi_ss_info(struct clk_mgr_internal *clk_mgr_dce)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

76

struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h

29

void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h

30

void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

191

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

293

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

316

void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

39

static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

86

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.h

29

void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

103

static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

125

int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

85

static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h

29

int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

37

void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.h

29

void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

104

void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

127

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

220

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

350

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

416

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

430

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

498

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

533

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

36

void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

42

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

53

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

180

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

88

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h

30

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

106

static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

135

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

253

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

286

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

440

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

519

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

551

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

708

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

89

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

45

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

134

int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

143

int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

167

int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

182

int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

197

void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

205

int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

219

void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

234

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

242

void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

250

int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

80

static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

99

static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

31

int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

32

int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

33

int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

34

int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

35

void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

36

int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

37

void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

38

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

39

void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

40

int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

102

static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

111

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

173

static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

197

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

333

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

364

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

386

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

398

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

407

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

417

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

438

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

463

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

474

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

528

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

588

void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

81

static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

92

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

96

void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

112

bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

126

bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

142

bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

161

bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

179

void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

187

void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

195

void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

203

void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

212

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

230

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

261

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

279

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

296

void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

304

void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

312

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

324

void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

332

void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

54

static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

77

static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

31

struct clk_mgr_internal;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

33

bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

34

bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

35

bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

36

bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

37

void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

38

void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

39

void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

40

void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

41

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

42

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

43

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

44

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

45

void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

46

void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

47

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

48

void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

49

void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

33

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

108

uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

53

static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

76

static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h

31

struct clk_mgr_internal;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h

33

uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

133

int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

145

int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

160

int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

176

int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

190

int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

204

int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

218

void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

230

void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

247

void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

255

void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

263

void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

271

void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

277

void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

80

static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

98

static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

150

int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

151

int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

152

int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

153

int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

154

int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

155

int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

156

void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

157

void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

158

void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

159

void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

160

void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

161

void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

162

void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

185

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

218

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

372

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

447

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

563

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

662

static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

768

void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

99

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

41

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

50

void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

142

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

261

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

293

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

485

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

506

static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

562

static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

643

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

810

void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

38

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

56

void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

103

static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

147

int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

156

int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

172

int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

189

int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

207

int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

225

int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

240

void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

255

void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

273

void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

284

void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

293

void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

302

void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

311

void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

320

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

350

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

85

static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

254

int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

255

int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

256

int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

257

int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

258

int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

259

int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

260

void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

261

void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

262

void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

263

void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

264

void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

265

void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

266

void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

268

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

269

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

179

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

189

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

213

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

340

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

372

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

556

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

577

static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

630

static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

779

static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

927

void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

41

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

66

void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

101

static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

119

static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

166

int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

175

int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

191

int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

208

int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

226

int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

244

int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

259

void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

274

void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

292

void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

303

void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

312

void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

321

void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

330

void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

339

void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

389

void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

100

void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

101

void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

102

void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

103

void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

104

void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

105

void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

107

void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

108

void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

93

int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

94

int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

95

int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

96

int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

97

int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

98

int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

99

void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

133

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

448

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

469

static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

490

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

597

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

740

void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

38

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

47

void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

114

static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

133

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

177

int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

186

int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

202

int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

220

int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

238

int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

253

void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

268

void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

286

void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

296

void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

305

void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

314

void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

323

void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

332

int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

344

int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

357

void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

114

int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

115

int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

116

int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

117

int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

118

int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

119

void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

120

void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

121

void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

122

void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

123

void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

124

void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

125

void dcn315_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

126

void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

127

int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

128

int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

129

void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

133

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

143

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

414

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

435

static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

492

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

684

void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

38

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

47

void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

100

static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

119

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

152

int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

161

int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

177

int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

195

int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

213

int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

228

void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

243

void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

261

void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

270

void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

279

void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

288

void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

297

void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

309

void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

320

int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

333

int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

122

int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

123

int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

124

int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

125

int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

126

int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

127

void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

128

void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

129

void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

130

void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

131

void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

132

void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

133

void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

134

void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

135

void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

136

int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

137

int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1013

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1034

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1045

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1107

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1117

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1123

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1133

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1161

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1241

void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

132

static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

155

static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

164

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

266

static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

309

static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

361

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

488

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

519

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

637

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

864

static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

892

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

955

static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

988

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

31

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

35

void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

38

void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

107

static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

129

static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

161

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

169

void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

177

void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

185

void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

194

static bool dcn32_get_hard_min_status_supported(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

210

static unsigned int dcn32_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

226

static bool dcn32_smu_wait_get_hard_min_status(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

281

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

303

void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

50

static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

72

static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

39

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

40

void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

41

void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

42

void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

43

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

44

void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1039

static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1229

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1238

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1254

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1321

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1603

void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

201

struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

202

struct dccg *dccg = clk_mgr_internal->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

256

static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

359

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

396

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

552

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

584

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

611

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

725

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

753

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

866

static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

942

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

963

static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

983

static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

45

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

61

void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

115

static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

136

static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

184

int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

193

int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

210

int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

227

int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

244

int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

261

int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

278

void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

294

void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

313

void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

325

void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

334

void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

343

void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

352

void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

361

void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

415

int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

430

int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

445

void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

457

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

469

int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

484

int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

500

void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

196

int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

197

int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

198

int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

199

int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

200

int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

201

int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

202

void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

203

void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

204

void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

205

void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

206

void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

207

void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

208

void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

210

void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

211

void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

212

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

214

int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

215

int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

216

int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

217

int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

218

void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1026

dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1074

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1090

struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1091

struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1123

if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1130

dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1194

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

120

static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1209

if (update_dppclk && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1274

static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1295

static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1328

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1353

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1386

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1393

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1401

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

144

static bool dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1475

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1485

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1492

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1509

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1525

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1571

struct clk_mgr_internal *dcn401_clk_mgr_construct(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1577

struct clk_mgr_internal *clk_mgr;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

159

static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1647

void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

218

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

316

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

337

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

413

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

525

static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

559

static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

593

static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

617

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

649

struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

650

struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

664

dcn401_smu_set_num_of_displays(clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

670

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

674

dcn401_smu_set_hard_min_by_freq(clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

681

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

685

dcn401_set_hard_min_by_freq_optimized(clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

691

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

697

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

703

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

709

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

714

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

719

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

724

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

729

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

734

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

739

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

746

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

75

static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

752

clk_mgr_internal,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

774

struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

775

struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

785

bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

786

dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

787

dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

788

dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

790

dcn401_is_df_throttle_opt_enabled(clk_mgr_internal);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

805

if (clk_mgr_internal->smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

837

if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

854

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

866

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

899

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

915

if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

923

if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

102

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

110

struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

113

void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

112

static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

146

bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

162

bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

181

bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

199

void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

207

void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

215

void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

223

void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

231

void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

239

void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

247

void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

255

static unsigned int dcn401_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

271

static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

301

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

321

void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

328

void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

336

bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

358

bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

37

static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

380

bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

398

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

406

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

414

unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

439

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

457

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

55

static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

92

static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

11

struct clk_mgr_internal;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

13

bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

14

bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

15

bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

16

void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

17

void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

18

void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

19

void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

20

void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

21

void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

22

void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

23

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

24

void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

25

void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

26

bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

29

bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

32

bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

35

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

36

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

37

unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

38

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

39

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1110

void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

116

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

157

void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

167

void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

216

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

373

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

400

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

507

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

533

void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

589

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

625

static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

703

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

767

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

792

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

852

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

882

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

897

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

901

void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

45

struct clk_mgr_internal base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

61

void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

78

void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

79

void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

82

void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn42_smu_dpm_clks *smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

83

void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

105

static uint32_t dcn42_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

127

static int dcn42_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

172

int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

181

int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

200

int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

218

int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

236

int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

254

void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

269

void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

288

void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

300

void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

309

void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

318

void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

327

void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

336

void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

390

int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

405

int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

420

void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

170

int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

171

int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

172

int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

173

int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

174

int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

175

void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

176

void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

177

void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

178

void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

179

void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

180

void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

181

void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

183

void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

184

void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

185

void dcn42_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

187

int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

188

int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

102

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

230

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

333

static void dcn42b_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

351

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

186

void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

32

void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

527

int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

528

int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

71

container_of(clk_mgr, struct clk_mgr_internal, base)