drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

367

clk_mgr->clk_mgr_mask = &disp_clk_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

51

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

61

static const struct clk_mgr_mask disp_clk_mask = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

274

clk_mgr->clk_mgr_mask = &disp_clk_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

50

static const struct clk_mgr_mask disp_clk_mask = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

194

clk_mgr->clk_mgr_mask = &disp_clk_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

52

static const struct clk_mgr_mask disp_clk_mask = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

44

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

547

clk_mgr->clk_mgr_mask = &clk_mgr_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

570

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

571

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

69

static const struct clk_mgr_mask clk_mgr_mask = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

190

clk_mgr->clk_mgr_mask = &clk_mgr_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

58

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

71

static const struct clk_mgr_mask clk_mgr_mask = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

184

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

185

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

50

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

539

clk_mgr->clk_mgr_mask = &clk_mgr_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

75

static const struct clk_mgr_mask clk_mgr_mask = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

110

static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1173

clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1177

clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

126

static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

86

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

879

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

880

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

118

static const struct clk_mgr_mask clk_mgr_mask_dcn351 = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

135

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn351;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

125

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1443

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

149

static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1286

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1287

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1587

clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn401;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

44

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

68

static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1054

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

48

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

81

static const struct clk_mgr_mask clk_mgr_mask_dcn42 = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

425

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42b;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

67

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

91

static const struct clk_mgr_mask clk_mgr_mask_dcn42b = {

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

455

const struct clk_mgr_mask *clk_mgr_mask;