clk32k
clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
return clocksource_register_hz(&clk32k, sclk_rate);
static struct clocksource clk32k = {
ret = clk_prepare_enable(twl6040->clk32k);
clk_disable_unprepare(twl6040->clk32k);
clk_disable_unprepare(twl6040->clk32k);
clk_disable_unprepare(twl6040->clk32k);
twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
if (IS_ERR(twl6040->clk32k)) {
if (PTR_ERR(twl6040->clk32k) == -EPROBE_DEFER)
twl6040->clk32k = NULL;
FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);
struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);
struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k);
rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk),
ret = devm_clk_hw_register(dev, &rtc->clk32k);
&rtc->clk32k);
struct clk_hw clk32k;
struct clk *clk32k;