drivers/block/zram/zram_drv.c

1633

char *compressor;

drivers/block/zram/zram_drv.c

1640

compressor = kstrdup(buf, GFP_KERNEL);

drivers/block/zram/zram_drv.c

1641

if (!compressor)

drivers/block/zram/zram_drv.c

1645

if (sz > 0 && compressor[sz - 1] == '\n')

drivers/block/zram/zram_drv.c

1646

compressor[sz - 1] = 0x00;

drivers/block/zram/zram_drv.c

1648

if (!zcomp_available_algorithm(compressor)) {

drivers/block/zram/zram_drv.c

1649

kfree(compressor);

drivers/block/zram/zram_drv.c

1655

kfree(compressor);

drivers/block/zram/zram_drv.c

1660

comp_algorithm_set(zram, prio, compressor);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1070

struct dm_compressor_info *compressor = &adev->dm.compressor;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1081

if (compressor->bo_ptr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1092

AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1093

&compressor->gpu_addr, &compressor->cpu_addr);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1098

adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

590

struct dm_compressor_info compressor;

drivers/gpu/drm/amd/display/dc/dc.h

1796

struct compressor *fbc_compressor;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

103

value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL));

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

106

dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

139

void dce110_compressor_power_up_fbc(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

145

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

149

if (compressor->options.bits.CLK_GATING_DISABLED == 1) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

157

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

160

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

164

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

167

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

169

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

175

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

176

compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

179

dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

182

dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

186

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

189

struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

191

if (compressor->options.bits.FBC_SUPPORT &&

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

192

(!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

198

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

205

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

208

compressor->is_enabled = true;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

212

compressor->attached_inst = params->inst + CONTROLLER_ID_D0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

216

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

219

misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

228

dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

232

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

238

void dce110_compressor_disable_fbc(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

240

struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

243

if (compressor->options.bits.FBC_SUPPORT) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

244

if (dce110_compressor_is_fbc_enabled_in_hw(compressor, &crtc_inst)) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

247

reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

249

dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

252

compressor->attached_inst = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

253

compressor->is_enabled = false;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

260

reset_lb_on_vblank(compressor,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

266

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

272

value = dm_read_reg(compressor->ctx, mmFBC_STATUS);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

275

*inst = compressor->attached_inst;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

279

value = dm_read_reg(compressor->ctx, mmFBC_MISC);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

281

value = dm_read_reg(compressor->ctx, mmFBC_CNTL);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

286

compressor->attached_inst;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

295

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

298

struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

302

compressor->compr_surface_address.addr.low_part;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

308

compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

311

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

315

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

317

compressor->compr_surface_address.addr.high_part);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

318

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

324

if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

331

dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

339

dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

344

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

351

uint32_t value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

358

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

385

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

391

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

394

struct compressor *dce110_compressor_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

406

void dce110_compressor_destroy(struct compressor **compressor)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

408

kfree(TO_DCE110_COMPRESSOR(*compressor));

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

409

*compressor = NULL;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

422

void dce110_compressor_construct(struct dce110_compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

426

compressor->base.options.raw = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

427

compressor->base.options.bits.FBC_SUPPORT = true;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

430

compressor->base.lpt_channels_num = 1;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

431

compressor->base.options.bits.DUMMY_BACKEND = false;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

439

compressor->base.options.bits.CLK_GATING_DISABLED = false;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

441

compressor->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

442

compressor->base.embedded_panel_h_size = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

443

compressor->base.embedded_panel_v_size = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

444

compressor->base.memory_bus_width = ctx->asic_id.vram_width;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

445

compressor->base.allocated_size = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

446

compressor->base.preferred_requested_size = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

447

compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

448

compressor->base.banks_num = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

449

compressor->base.raw_size = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

450

compressor->base.channel_interleave_size = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

451

compressor->base.dram_channels_num = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

452

compressor->base.lpt_channels_num = 0;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

453

compressor->base.attached_inst = CONTROLLER_ID_UNDEFINED;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

454

compressor->base.is_enabled = false;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

455

compressor->base.funcs = &dce110_compressor_funcs;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

70

static void reset_lb_on_vblank(struct compressor *compressor, uint32_t crtc_inst)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

76

struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

80

status_pos = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION));

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

84

if (status_pos != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION))) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

86

value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL));

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

89

dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

91

frame_count = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT));

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

95

if (frame_count != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT)))

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

30

#define TO_DCE110_COMPRESSOR(compressor)\

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

31

container_of(compressor, struct dce110_compressor, base)

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

39

struct compressor base;

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

43

struct compressor *dce110_compressor_create(struct dc_context *ctx);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

48

void dce110_compressor_destroy(struct compressor **cp);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

51

void dce110_compressor_power_up_fbc(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

53

void dce110_compressor_enable_fbc(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

56

void dce110_compressor_disable_fbc(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

58

void dce110_compressor_set_fbc_invalidation_triggers(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

62

struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

65

bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

69

void dce110_compressor_enable_lpt(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

71

void dce110_compressor_disable_lpt(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

73

void dce110_compressor_program_lpt_control(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h

76

bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

316

void dce112_compressor_power_up_fbc(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

322

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

326

if (compressor->options.bits.CLK_GATING_DISABLED == 1) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

334

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

337

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

341

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

344

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

346

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

352

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

353

compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

356

dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

359

dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

363

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

367

struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

369

if (compressor->options.bits.FBC_SUPPORT &&

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

370

(compressor->options.bits.DUMMY_BACKEND == 0) &&

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

371

(!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

383

if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

387

dce112_compressor_enable_lpt(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

391

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

397

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

400

compressor->is_enabled = true;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

401

compressor->attached_inst = params->inst;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

406

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

408

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

414

void dce112_compressor_disable_fbc(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

416

struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

418

if (compressor->options.bits.FBC_SUPPORT &&

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

419

dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

422

reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

424

dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

427

compressor->attached_inst = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

428

compressor->is_enabled = false;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

432

if (compressor->options.bits.LPT_SUPPORT)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

433

dce112_compressor_disable_lpt(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

440

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

446

value = dm_read_reg(compressor->ctx, mmFBC_STATUS);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

449

*inst = compressor->attached_inst;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

453

value = dm_read_reg(compressor->ctx, mmFBC_MISC);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

455

value = dm_read_reg(compressor->ctx, mmFBC_CNTL);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

460

compressor->attached_inst;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

467

bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

470

uint32_t value = dm_read_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

480

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

483

struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

487

compressor->compr_surface_address.addr.low_part;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

491

compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

494

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

497

if (compressor->options.bits.LPT_SUPPORT) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

509

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

511

compressor->compr_surface_address.addr.high_part);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

512

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

520

if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

528

dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

536

dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

540

void dce112_compressor_disable_lpt(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

542

struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

551

compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

559

compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

565

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

571

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

575

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

581

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

585

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

591

dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

594

void dce112_compressor_enable_lpt(struct compressor *compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

596

struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

603

value = dm_read_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

610

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

615

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

621

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

627

value_control = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

633

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

640

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

644

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

650

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

654

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

657

struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

664

if (!compressor->options.bits.LPT_SUPPORT)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

667

lpt_control = dm_read_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

675

switch (compressor->lpt_channels_num) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

722

dm_write_reg(compressor->ctx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

731

struct compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

738

uint32_t value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

745

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

772

value = dm_read_reg(compressor->ctx, addr);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

784

dm_write_reg(compressor->ctx, addr, value);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

787

void dce112_compressor_construct(struct dce112_compressor *compressor,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

793

compressor->base.options.raw = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

794

compressor->base.options.bits.FBC_SUPPORT = true;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

795

compressor->base.options.bits.LPT_SUPPORT = true;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

797

compressor->base.lpt_channels_num = 1;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

798

compressor->base.options.bits.DUMMY_BACKEND = false;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

802

if (compressor->base.memory_bus_width == 64)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

803

compressor->base.options.bits.LPT_SUPPORT = false;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

805

compressor->base.options.bits.CLK_GATING_DISABLED = false;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

807

compressor->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

808

compressor->base.embedded_panel_h_size = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

809

compressor->base.embedded_panel_v_size = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

810

compressor->base.memory_bus_width = ctx->asic_id.vram_width;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

811

compressor->base.allocated_size = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

812

compressor->base.preferred_requested_size = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

813

compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

814

compressor->base.banks_num = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

815

compressor->base.raw_size = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

816

compressor->base.channel_interleave_size = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

817

compressor->base.dram_channels_num = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

818

compressor->base.lpt_channels_num = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

819

compressor->base.attached_inst = 0;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

820

compressor->base.is_enabled = false;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

824

compressor->base.embedded_panel_h_size =

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

826

compressor->base.embedded_panel_v_size =

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

831

struct compressor *dce112_compressor_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

843

void dce112_compressor_destroy(struct compressor **compressor)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

845

kfree(TO_DCE112_COMPRESSOR(*compressor));

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

846

*compressor = NULL;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

30

#define TO_DCE112_COMPRESSOR(compressor)\

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

31

container_of(compressor, struct dce112_compressor, base)

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

39

struct compressor base;

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

43

struct compressor *dce112_compressor_create(struct dc_context *ctx);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

48

void dce112_compressor_destroy(struct compressor **cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

51

void dce112_compressor_power_up_fbc(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

53

void dce112_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

56

void dce112_compressor_disable_fbc(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

58

void dce112_compressor_set_fbc_invalidation_triggers(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

62

struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

65

bool dce112_compressor_is_fbc_enabled_in_hw(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

69

void dce112_compressor_enable_lpt(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

71

void dce112_compressor_disable_lpt(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

73

void dce112_compressor_program_lpt_control(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h

76

bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2267

struct compressor *compr = dc->fbc_compressor;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

123

struct compressor *compr = dc->fbc_compressor;

drivers/gpu/drm/amd/display/dc/inc/compressor.h

62

struct compressor;

drivers/gpu/drm/amd/display/dc/inc/compressor.h

66

void (*power_up_fbc)(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/inc/compressor.h

67

void (*enable_fbc)(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/inc/compressor.h

69

void (*disable_fbc)(struct compressor *cp);

drivers/gpu/drm/amd/display/dc/inc/compressor.h

70

void (*set_fbc_invalidation_triggers)(struct compressor *cp,

drivers/gpu/drm/amd/display/dc/inc/compressor.h

73

struct compressor *cp,

drivers/gpu/drm/amd/display/dc/inc/compressor.h

75

bool (*is_fbc_enabled_in_hw)(struct compressor *cp,

drivers/net/ppp/bsd_comp.c

1131

static struct compressor ppp_bsd_compress = {

drivers/net/ppp/bsd_comp.c

192

extern int ppp_register_compressor (struct compressor *cp);

drivers/net/ppp/bsd_comp.c

193

extern void ppp_unregister_compressor (struct compressor *cp);

drivers/net/ppp/ppp_deflate.c

564

extern int ppp_register_compressor (struct compressor *cp);

drivers/net/ppp/ppp_deflate.c

565

extern void ppp_unregister_compressor (struct compressor *cp);

drivers/net/ppp/ppp_deflate.c

570

static struct compressor ppp_deflate = {

drivers/net/ppp/ppp_deflate.c

588

static struct compressor ppp_deflate_draft = {

drivers/net/ppp/ppp_generic.c

138

struct compressor *xcomp; /* transmit packet compressor 8c */

drivers/net/ppp/ppp_generic.c

140

struct compressor *rcomp; /* receive decompressor 94 */

drivers/net/ppp/ppp_generic.c

286

static struct compressor *find_compressor(int type);

drivers/net/ppp/ppp_generic.c

3070

struct compressor *cp, *ocomp;

drivers/net/ppp/ppp_generic.c

3224

struct compressor *xcomp, *rcomp;

drivers/net/ppp/ppp_generic.c

3254

struct compressor *comp;

drivers/net/ppp/ppp_generic.c

3271

ppp_register_compressor(struct compressor *cp)

drivers/net/ppp/ppp_generic.c

3293

ppp_unregister_compressor(struct compressor *cp)

drivers/net/ppp/ppp_generic.c

3307

static struct compressor *

drivers/net/ppp/ppp_generic.c

3311

struct compressor *cp = NULL;

drivers/net/ppp/ppp_mppe.c

576

static struct compressor ppp_mppe = {

include/linux/ppp-comp.h

101

extern int ppp_register_compressor(struct compressor *);

include/linux/ppp-comp.h

102

extern void ppp_unregister_compressor(struct compressor *);

kernel/power/hibernate.c

1505

static int hibernate_compressor_param_set(const char *compressor,

kernel/power/hibernate.c

1513

index = sysfs_match_string(comp_alg_enabled, compressor);

kernel/power/hibernate.c

1526

compressor);

kernel/power/hibernate.c

1541

module_param_cb(compressor, &hibernate_compressor_param_ops,

kernel/power/hibernate.c

1543

MODULE_PARM_DESC(compressor,

mm/zswap.c

108

module_param_cb(compressor, &zswap_compressor_param_ops,

mm/zswap.c

245

static struct zswap_pool *zswap_pool_create(char *compressor)

mm/zswap.c

251

if (!zswap_has_pool && !strcmp(compressor, ZSWAP_PARAM_UNSET))

mm/zswap.c

264

strscpy(pool->tfm_name, compressor, sizeof(pool->tfm_name));

mm/zswap.c

422

static struct zswap_pool *zswap_pool_find_get(char *compressor)

mm/zswap.c

429

if (strcmp(pool->tfm_name, compressor))