cnic_ctx_wr
cnic_ctx_wr(dev, 45, 0, seed);
cnic_ctx_wr(dev, cid_addr, i, 0);
cnic_ctx_wr(dev, cid_addr2, i, 0);
cnic_ctx_wr(dev, cid_addr, offset0, val);
cnic_ctx_wr(dev, cid_addr, offset1, val);
cnic_ctx_wr(dev, cid_addr, offset2, val);
cnic_ctx_wr(dev, cid_addr, offset3, val);
cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);