check_hw_ready
if (!check_hw_ready(rtwdev, bcn_valid_addr, bcn_valid_mask, 1)) {
if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1))
if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
if (!check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55))
if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
!check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
EXPORT_SYMBOL(check_hw_ready);
if (!check_hw_ready(rtwdev, ltecoex->ctrl, LTECOEX_READY, 1))
if (!check_hw_ready(rtwdev, ltecoex->ctrl, LTECOEX_READY, 1))
ret = check_hw_ready(rtwdev, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1, 0);
if (!check_hw_ready(rtwdev, REG_RXPKT_NUM, BIT_RXDMA_IDLE, 1))
if (!check_hw_ready(rtwdev, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1, 0))