drivers/gpu/drm/mediatek/mtk_crtc.c

486

struct cmdq_pkt *cmdq_handle)

drivers/gpu/drm/mediatek/mtk_crtc.c

56

struct cmdq_pkt cmdq_handle;

drivers/gpu/drm/mediatek/mtk_crtc.c

561

struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

100

if (cmdq_pkt) {

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

101

cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

130

unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

137

mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

138

mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

139

mtk_ddp_write(cmdq_pkt,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

144

mtk_ddp_write(cmdq_pkt,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

150

mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

156

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

160

mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

161

mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

164

DITHER_ENGINE_EN, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

182

unsigned int cfg, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

187

DISP_DITHERING, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

192

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

197

mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

199

mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

201

mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

222

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

226

mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

227

mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

228

mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

240

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

244

mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

246

mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

69

void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

74

if (cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

75

cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

82

void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

87

if (cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

88

cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

95

void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

146

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

149

comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

224

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

227

comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

356

void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

359

void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

362

void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

50

struct cmdq_pkt;

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

58

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

74

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_aal.c

69

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_aal.c

77

mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE);

drivers/gpu/drm/mediatek/mtk_disp_aal.c

78

mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE);

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

103

mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

105

mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

107

mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

109

mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

111

mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

59

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

63

mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs,

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

65

mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,

drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

91

struct cmdq_pkt *cmdq_pkt = NULL;

drivers/gpu/drm/mediatek/mtk_disp_color.c

62

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_color.c

66

mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color));

drivers/gpu/drm/mediatek/mtk_disp_color.c

67

mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color));

drivers/gpu/drm/mediatek/mtk_disp_drv.h

124

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

127

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

148

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

152

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

168

void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

169

void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

171

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

19

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

30

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

39

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

44

unsigned int dither_en, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

58

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

68

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

73

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

74

void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

75

void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

86

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

91

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

94

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_drv.h

96

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

211

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

219

mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE);

drivers/gpu/drm/mediatek/mtk_disp_gamma.c

222

DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_merge.c

100

mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

103

mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

106

if (!cmdq_pkt && priv->async_clk)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

111

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

113

mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

116

mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

120

mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

124

mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

131

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

133

mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_merge.c

138

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

149

mtk_merge_fifo_setting(priv, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_merge.c

156

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

158

mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

160

mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

170

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

173

mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

176

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

183

mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

185

mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

188

mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

190

mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

83

void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_merge.c

88

mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

91

mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

95

void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

288

static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

291

mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

297

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

308

mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx),

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

315

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

320

mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

327

mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

330

mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

331

mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

369

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

376

mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

387

mtk_ddp_write(cmdq_pkt, gmc_value,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

389

mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

394

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

398

mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

400

mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

473

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

480

mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

482

mtk_ddp_write_relaxed(cmdq_pkt,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

485

mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

488

mtk_ddp_write_relaxed(cmdq_pkt, pitch_msb,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

495

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

510

mtk_ovl_layer_off(dev, idx, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

553

mtk_ovl_set_afbc(ovl, cmdq_pkt, idx,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

556

mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

558

mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

560

mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

562

mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

564

mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

568

mtk_ovl_afbc_layer_config(ovl, idx, pending, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

570

mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

571

mtk_ovl_layer_on(dev, idx, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

134

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

161

mtk_merge_stop_cmdq(merge, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

162

mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

163

mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

164

mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

180

mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

182

pending->height, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

190

mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

195

mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

198

mtk_merge_start_cmdq(merge, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

200

mtk_mdp_rdma_start(rdma_l, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

202

mtk_mdp_rdma_start(rdma_r, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

204

mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

206

mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

211

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

216

vrefresh, bpc, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

186

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

193

mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

195

mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

213

mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

260

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

270

mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

273

mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

276

mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

280

mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

284

mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

286

mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

288

mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

290

mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

157

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ethdr.c

178

mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

204

MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ethdr.c

206

mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

208

mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

209

mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

210

mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,

drivers/gpu/drm/mediatek/mtk_ethdr.c

216

unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_ethdr.c

228

mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

231

mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

234

mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

237

mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

240

mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

243

mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);

drivers/gpu/drm/mediatek/mtk_ethdr.c

244

mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);

drivers/gpu/drm/mediatek/mtk_ethdr.c

245

mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);

drivers/gpu/drm/mediatek/mtk_ethdr.c

246

mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);

drivers/gpu/drm/mediatek/mtk_ethdr.c

247

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

249

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

251

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

253

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

255

mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));

drivers/gpu/drm/mediatek/mtk_ethdr.c

256

mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,

drivers/gpu/drm/mediatek/mtk_ethdr.c

258

mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

261

mtk_mmsys_hdr_config(priv->mmsys_dev, w / 2, h, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ethdr.c

262

mtk_mmsys_mixer_in_channel_swap(priv->mmsys_dev, 4, 0, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ethdr.h

15

unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_ethdr.h

19

struct cmdq_pkt *cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

149

static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

153

mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

161

void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

165

mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

169

void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

173

mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

175

mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

176

mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

180

struct cmdq_pkt *cmdq_pkt)

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

188

mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

190

mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

192

mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

196

mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

199

mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

202

mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

205

mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

208

mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

210

mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

212

mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

215

mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg->color_encoding) << 23,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

218

mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

223

mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

225

mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

227

mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

229

mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

231

mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,

drivers/mailbox/mtk-cmdq-mailbox.c

449

struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;

drivers/mailbox/mtk-cmdq-mailbox.c

81

struct cmdq_pkt *pkt; /* the packet sent from mailbox client */

drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h

27

struct cmdq_pkt pkt;

drivers/soc/mediatek/mtk-cmdq-helper.c

147

int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size)

drivers/soc/mediatek/mtk-cmdq-helper.c

174

void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt)

drivers/soc/mediatek/mtk-cmdq-helper.c

182

static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,

drivers/soc/mediatek/mtk-cmdq-helper.c

209

static int cmdq_pkt_mask(struct cmdq_pkt *pkt, u32 mask)

drivers/soc/mediatek/mtk-cmdq-helper.c

218

int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)

drivers/soc/mediatek/mtk-cmdq-helper.c

230

int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base,

drivers/soc/mediatek/mtk-cmdq-helper.c

243

int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/,

drivers/soc/mediatek/mtk-cmdq-helper.c

250

int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,

drivers/soc/mediatek/mtk-cmdq-helper.c

267

int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base,

drivers/soc/mediatek/mtk-cmdq-helper.c

281

int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/,

drivers/soc/mediatek/mtk-cmdq-helper.c

288

int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,

drivers/soc/mediatek/mtk-cmdq-helper.c

302

int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

drivers/soc/mediatek/mtk-cmdq-helper.c

316

int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

drivers/soc/mediatek/mtk-cmdq-helper.c

336

int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,

drivers/soc/mediatek/mtk-cmdq-helper.c

349

int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,

drivers/soc/mediatek/mtk-cmdq-helper.c

368

int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr)

drivers/soc/mediatek/mtk-cmdq-helper.c

396

int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)

drivers/soc/mediatek/mtk-cmdq-helper.c

412

int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event)

drivers/soc/mediatek/mtk-cmdq-helper.c

427

int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)

drivers/soc/mediatek/mtk-cmdq-helper.c

442

int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)

drivers/soc/mediatek/mtk-cmdq-helper.c

457

int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,

drivers/soc/mediatek/mtk-cmdq-helper.c

470

int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,

drivers/soc/mediatek/mtk-cmdq-helper.c

484

int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask)

drivers/soc/mediatek/mtk-cmdq-helper.c

529

int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, u16 result_reg_idx,

drivers/soc/mediatek/mtk-cmdq-helper.c

553

int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)

drivers/soc/mediatek/mtk-cmdq-helper.c

565

int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)

drivers/soc/mediatek/mtk-cmdq-helper.c

576

int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)

drivers/soc/mediatek/mtk-cmdq-helper.c

586

int cmdq_pkt_eoc(struct cmdq_pkt *pkt)

drivers/soc/mediatek/mtk-mmsys.c

164

struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

169

if (mmsys->cmdq_base.size && cmdq_pkt) {

drivers/soc/mediatek/mtk-mmsys.c

170

ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,

drivers/soc/mediatek/mtk-mmsys.c

217

struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

220

~0, height << 16 | width, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

225

struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

228

be_height << 16 | be_width, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

233

u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

238

alpha << 16 | alpha, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

239

mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

241

alpha_sel << (19 + idx), cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

243

GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

248

struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

251

BIT(4), channel_swap << 4, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

282

struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

298

mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

303

struct cmdq_pkt *cmdq_pkt)

drivers/soc/mediatek/mtk-mmsys.c

310

((enable) ? client : 0), cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

313

((enable) ? client : 0), cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

318

((enable) ? client : 0), cmdq_pkt);

drivers/soc/mediatek/mtk-mmsys.c

321

((enable) ? client : 0), cmdq_pkt);

drivers/soc/mediatek/mtk-mutex.c

1001

cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,

drivers/soc/mediatek/mtk-mutex.c

992

struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;

include/linux/mailbox/mtk-cmdq-mailbox.h

70

struct cmdq_pkt *pkt;

include/linux/soc/mediatek/mtk-cmdq.h

118

int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size);

include/linux/soc/mediatek/mtk-cmdq.h

125

void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt);

include/linux/soc/mediatek/mtk-cmdq.h

136

int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);

include/linux/soc/mediatek/mtk-cmdq.h

148

int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,

include/linux/soc/mediatek/mtk-cmdq.h

161

int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

174

int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

188

int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,

include/linux/soc/mediatek/mtk-cmdq.h

202

int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

214

int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,

include/linux/soc/mediatek/mtk-cmdq.h

231

int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

249

int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

262

int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

277

int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

28

struct cmdq_pkt;

include/linux/soc/mediatek/mtk-cmdq.h

290

int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr);

include/linux/soc/mediatek/mtk-cmdq.h

300

int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);

include/linux/soc/mediatek/mtk-cmdq.h

315

int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event);

include/linux/soc/mediatek/mtk-cmdq.h

324

int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);

include/linux/soc/mediatek/mtk-cmdq.h

333

int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event);

include/linux/soc/mediatek/mtk-cmdq.h

348

int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

365

int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

380

int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, u16 result_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

396

int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);

include/linux/soc/mediatek/mtk-cmdq.h

412

int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask);

include/linux/soc/mediatek/mtk-cmdq.h

426

int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa);

include/linux/soc/mediatek/mtk-cmdq.h

429

static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)

include/linux/soc/mediatek/mtk-cmdq.h

446

int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa);

include/linux/soc/mediatek/mtk-cmdq.h

460

int cmdq_pkt_eoc(struct cmdq_pkt *pkt);

include/linux/soc/mediatek/mtk-cmdq.h

477

static inline int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size)

include/linux/soc/mediatek/mtk-cmdq.h

482

static inline void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt) { }

include/linux/soc/mediatek/mtk-cmdq.h

484

static inline int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)

include/linux/soc/mediatek/mtk-cmdq.h

489

static inline int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,

include/linux/soc/mediatek/mtk-cmdq.h

495

static inline int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

501

static inline int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

507

static inline int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,

include/linux/soc/mediatek/mtk-cmdq.h

513

static inline int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

520

static inline int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

526

static inline int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

532

static inline int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

538

static inline int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

544

static inline int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,

include/linux/soc/mediatek/mtk-cmdq.h

550

static inline int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)

include/linux/soc/mediatek/mtk-cmdq.h

555

static inline int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)

include/linux/soc/mediatek/mtk-cmdq.h

560

static inline int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)

include/linux/soc/mediatek/mtk-cmdq.h

565

static inline int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

571

static inline int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,

include/linux/soc/mediatek/mtk-cmdq.h

577

static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)

include/linux/soc/mediatek/mtk-cmdq.h

582

static inline int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask)

include/linux/soc/mediatek/mtk-cmdq.h

587

static inline int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)

include/linux/soc/mediatek/mtk-cmdq.h

592

static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa)

include/linux/soc/mediatek/mtk-cmdq.h

597

static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)

include/linux/soc/mediatek/mtk-cmdq.h

602

static inline int cmdq_pkt_eoc(struct cmdq_pkt *pkt)

include/linux/soc/mediatek/mtk-cmdq.h

67

int (*pkt_write)(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base,

include/linux/soc/mediatek/mtk-cmdq.h

69

int (*pkt_write_mask)(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base,

include/linux/soc/mediatek/mtk-mmsys.h

101

struct cmdq_pkt *cmdq_pkt);

include/linux/soc/mediatek/mtk-mmsys.h

104

u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);

include/linux/soc/mediatek/mtk-mmsys.h

107

struct cmdq_pkt *cmdq_pkt);

include/linux/soc/mediatek/mtk-mmsys.h

110

struct cmdq_pkt *cmdq_pkt);

include/linux/soc/mediatek/mtk-mmsys.h

113

struct cmdq_pkt *cmdq_pkt);

include/linux/soc/mediatek/mtk-mmsys.h

98

int height, struct cmdq_pkt *cmdq_pkt);