drivers/accel/ivpu/ivpu_jsm_msg.c

287

u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size)

drivers/accel/ivpu/ivpu_jsm_msg.c

298

req.payload.hws_create_cmdq.cmdq_base = cmdq_base;

drivers/accel/ivpu/ivpu_jsm_msg.c

327

u64 cmdq_base, u32 cmdq_size)

drivers/accel/ivpu/ivpu_jsm_msg.c

336

req.payload.hws_register_db.cmdq_base = cmdq_base;

drivers/accel/ivpu/ivpu_jsm_msg.h

27

u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size);

drivers/accel/ivpu/ivpu_jsm_msg.h

30

u64 cmdq_base, u32 cmdq_size);

drivers/accel/ivpu/vpu_jsm_api.h

1168

u64 cmdq_base;

drivers/accel/ivpu/vpu_jsm_api.h

1257

u64 cmdq_base;

drivers/gpu/drm/mediatek/mtk_ethdr.c

178

mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

206

mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

208

mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

209

mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));

drivers/gpu/drm/mediatek/mtk_ethdr.c

210

mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,

drivers/gpu/drm/mediatek/mtk_ethdr.c

228

mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

231

mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

234

mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

237

mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

240

mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,

drivers/gpu/drm/mediatek/mtk_ethdr.c

243

mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);

drivers/gpu/drm/mediatek/mtk_ethdr.c

244

mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);

drivers/gpu/drm/mediatek/mtk_ethdr.c

245

mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);

drivers/gpu/drm/mediatek/mtk_ethdr.c

246

mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);

drivers/gpu/drm/mediatek/mtk_ethdr.c

247

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

249

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

251

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

253

mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

255

mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));

drivers/gpu/drm/mediatek/mtk_ethdr.c

257

&mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);

drivers/gpu/drm/mediatek/mtk_ethdr.c

258

mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

337

&priv->ethdr_comp[i].cmdq_base, i);

drivers/gpu/drm/mediatek/mtk_ethdr.c

73

struct cmdq_client_reg cmdq_base;

drivers/infiniband/hw/bng_re/bng_fw.c

711

bng_re_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bng_re/bng_fw.c

746

bng_re_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bng_re/bng_fw.h

132

struct cmdq_base *req;

drivers/infiniband/hw/bng_re/bng_fw.h

140

static inline void bng_re_rcfw_cmd_prep(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_fw.h

163

static inline u32 bng_re_get_cmd_slots(struct cmdq_base *req)

drivers/infiniband/hw/bng_re/bng_fw.h

179

static inline u32 bng_re_set_cmd_slots(struct cmdq_base *req)

drivers/infiniband/hw/bng_re/bng_sp.c

27

bng_re_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bng_re/bng_sp.c

53

bng_re_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bng_re/bng_tlv.h

102

static inline void __set_cmdq_base_cmd_size(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_tlv.h

106

((struct cmdq_base *)GET_TLV_DATA(req))->cmd_size = val;

drivers/infiniband/hw/bng_re/bng_tlv.h

111

static inline __le16 __get_cmdq_base_flags(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bng_re/bng_tlv.h

114

return ((struct cmdq_base *)GET_TLV_DATA(req))->flags;

drivers/infiniband/hw/bng_re/bng_tlv.h

119

static inline void __set_cmdq_base_flags(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_tlv.h

123

((struct cmdq_base *)GET_TLV_DATA(req))->flags = val;

drivers/infiniband/hw/bng_re/bng_tlv.h

26

static inline u8 __get_cmdq_base_opcode(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bng_re/bng_tlv.h

29

return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode;

drivers/infiniband/hw/bng_re/bng_tlv.h

34

static inline void __set_cmdq_base_opcode(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_tlv.h

38

((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val;

drivers/infiniband/hw/bng_re/bng_tlv.h

43

static inline __le16 __get_cmdq_base_cookie(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bng_re/bng_tlv.h

46

return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie;

drivers/infiniband/hw/bng_re/bng_tlv.h

51

static inline void __set_cmdq_base_cookie(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_tlv.h

55

((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val;

drivers/infiniband/hw/bng_re/bng_tlv.h

60

static inline __le64 __get_cmdq_base_resp_addr(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bng_re/bng_tlv.h

63

return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr;

drivers/infiniband/hw/bng_re/bng_tlv.h

68

static inline void __set_cmdq_base_resp_addr(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_tlv.h

72

((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr = val;

drivers/infiniband/hw/bng_re/bng_tlv.h

77

static inline u8 __get_cmdq_base_resp_size(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bng_re/bng_tlv.h

80

return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_size;

drivers/infiniband/hw/bng_re/bng_tlv.h

85

static inline void __set_cmdq_base_resp_size(struct cmdq_base *req,

drivers/infiniband/hw/bng_re/bng_tlv.h

89

((struct cmdq_base *)GET_TLV_DATA(req))->resp_size = val;

drivers/infiniband/hw/bng_re/bng_tlv.h

94

static inline u8 __get_cmdq_base_cmd_size(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bnxt_re/qplib_fp.c

1319

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

1463

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

1597

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

2230

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

2317

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

2354

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

627

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

663

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

728

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

831

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_fp.c

977

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

459

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

463

msg.req = (struct cmdq_base *)&req;

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

818

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

841

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

113

static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req)

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

243

struct cmdq_base *req;

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

63

static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

97

static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req)

drivers/infiniband/hw/bnxt_re/qplib_sp.c

106

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

1062

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

1122

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

1140

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

216

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

285

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

355

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

420

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

465

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

491

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

526

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

564

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

623

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

721

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

78

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

811

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

921

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC,

drivers/infiniband/hw/bnxt_re/qplib_sp.c

982

bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

102

return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_size;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

107

static inline void __set_cmdq_base_resp_size(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

111

((struct cmdq_base *)GET_TLV_DATA(req))->resp_size = val;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

116

static inline u8 __get_cmdq_base_cmd_size(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

124

static inline void __set_cmdq_base_cmd_size(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

128

((struct cmdq_base *)GET_TLV_DATA(req))->cmd_size = val;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

133

static inline __le16 __get_cmdq_base_flags(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

136

return ((struct cmdq_base *)GET_TLV_DATA(req))->flags;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

141

static inline void __set_cmdq_base_flags(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

145

((struct cmdq_base *)GET_TLV_DATA(req))->flags = val;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

48

static inline u8 __get_cmdq_base_opcode(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

51

return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

56

static inline void __set_cmdq_base_opcode(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

60

((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

65

static inline __le16 __get_cmdq_base_cookie(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

68

return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

73

static inline void __set_cmdq_base_cookie(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

77

((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

82

static inline __le64 __get_cmdq_base_resp_addr(struct cmdq_base *req, u32 size)

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

85

return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

90

static inline void __set_cmdq_base_resp_addr(struct cmdq_base *req,

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

94

((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr = val;

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

99

static inline u8 __get_cmdq_base_resp_size(struct cmdq_base *req, u32 size)

drivers/soc/mediatek/mtk-mmsys.c

160

struct cmdq_client_reg cmdq_base;

drivers/soc/mediatek/mtk-mmsys.c

169

if (mmsys->cmdq_base.size && cmdq_pkt) {

drivers/soc/mediatek/mtk-mmsys.c

170

ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,

drivers/soc/mediatek/mtk-mmsys.c

171

mmsys->cmdq_base.offset + offset, val,

drivers/soc/mediatek/mtk-mmsys.c

423

ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

117

test_data.cmdq_base, SZ_64K);

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

191

vm_paddr_t cmdq_base;

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

201

cmdq_base = vm_phy_pages_alloc(vm, pages_per_64k, gpa_base,

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

203

virt_map(vm, cmdq_base, cmdq_base, pages_per_64k);

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

204

test_data.cmdq_base = cmdq_base;

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

205

test_data.cmdq_base_va = (void *)cmdq_base;

tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c

40

vm_paddr_t cmdq_base;

tools/testing/selftests/kvm/include/arm64/gic_v3_its.h

12

void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base,

tools/testing/selftests/kvm/include/arm64/gic_v3_its.h

14

void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid);

tools/testing/selftests/kvm/include/arm64/gic_v3_its.h

15

void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id,

tools/testing/selftests/kvm/include/arm64/gic_v3_its.h

17

void its_send_invall_cmd(void *cmdq_base, u32 collection_id);

tools/testing/selftests/kvm/include/arm64/gic_v3_its.h

18

void its_send_sync_cmd(void *cmdq_base, u32 vcpu_id);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

175

static void its_send_cmd(void *cmdq_base, struct its_cmd_block *cmd)

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

178

struct its_cmd_block *dst = cmdq_base + cwriter;

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

207

void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base,

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

218

its_send_cmd(cmdq_base, &cmd);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

221

void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid)

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

230

its_send_cmd(cmdq_base, &cmd);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

233

void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id,

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

244

its_send_cmd(cmdq_base, &cmd);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

247

void its_send_invall_cmd(void *cmdq_base, u32 collection_id)

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

254

its_send_cmd(cmdq_base, &cmd);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

257

void its_send_sync_cmd(void *cmdq_base, u32 vcpu_id)

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

264

its_send_cmd(cmdq_base, &cmd);