channel_width
mem_channel_width = le32_to_cpu(umc_info->v40.channel_width);
mem_channel_width = vram_info->v30.channel_width;
mem_channel_width = vram_module->v9.channel_width;
mem_channel_width = vram_module->v10.channel_width;
mem_channel_width = vram_module->v11.channel_width;
mem_channel_width = vram_module->v9.channel_width;
info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8;
uint8_t channel_width;
uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
uint8_t channel_width;
uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
qi->channel_width = 64;
qi->channel_width = 32;
qi->channel_width = 16;
qi->channel_width = 32;
qi->channel_width = 64;
qi->channel_width = 32;
qi->channel_width = 32;
qi->channel_width = 16;
static int tgl_peakbw(int num_channels, int channel_width, int dclk)
return num_channels * (channel_width / 8) * dclk;
peakbw = tgl_peakbw(num_channels, qi.channel_width, icl_sagv_max_dclk(&qi));
u8 channel_width;
bi->peakbw[j] = tgl_peakbw(num_channels, qi.channel_width, sp->dclk);
peakbw = tgl_peakbw(num_channels, qi.channel_width, icl_sagv_max_dclk(&qi));
int bw = tgl_peakbw(num_channels, qi.channel_width, sp->dclk);
struct mvm_statistics_tx_channel_width channel_width;
struct mvm_statistics_tx_channel_width channel_width;
u8 prev_bw = common->channel_width;
common->channel_width = BW_20MHZ;
common->channel_width = BW_40MHZ;
if (common->channel_width)
if (common->channel_width)
if (common->channel_width != prev_bw) {
if (common->channel_width == BW_40MHZ)
chan_cfg->channel_width = 0x1;
if (common->channel_width == BW_40MHZ)
common->channel_width = BW_20MHZ;
if (common->channel_width == BW_40MHZ) {
common->channel_width == BW_20MHZ)
vap_caps->channel_bw = common->channel_width;
if (common->channel_width == BW_40MHZ) {
if (common->channel_width == BW_40MHZ) {
u8 channel_width;
u8 channel_width;
enum channel_width BandWidth,
enum channel_width BandWidth,
static s16 get_bandwidth_idx(const enum channel_width bandwidth)
enum channel_width bandwidth,
enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
enum channel_width BandWidth,
struct adapter *Adapter, enum channel_width CurrentBW
enum channel_width ChnlWidth,
enum channel_width tmpBW = pHalData->CurrentChannelBW;
enum channel_width Bandwidth,
struct adapter *Adapter, enum channel_width Bandwidth
enum channel_width BandWidth, u8 Channel,
enum channel_width BandWidth, u8 Channel);
enum channel_width Bandwidth, u8 RfPath, u8 DataRate,
enum channel_width CurrentChannelBW;
void rtw_hal_set_chnl_bw(struct adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
enum channel_width BandWidth, u8 Channel);
enum channel_width Bandwidth,
enum channel_width Bandwidth);
__field(u32, channel_width)
__entry->channel_width = link_conf->chanreq.oper.width;