clock_out
clock_out(bus, !read);
clock_out(bus, (addr & 0x10) != 0);
clock_out(bus, (reg & 0x10) != 0);
clock_out(bus, 1);
clock_out(bus, 0);
clock_out(bus, 1);
clock_out(bus, read);
pdata.clk_out = cfg->clock_out;
dev->config.clock_out = pdata->clk_out;
switch (dev->cfg->clock_out) {
u8 clock_out;
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = 0,
.clock_out = 0,
.clock_out = 0,
if (priv->cfg->clock_out) {
bool clock_out;
mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30);
(priv->cfg->clock_out << 6) | 0x33);
(priv->cfg->clock_out << 6) | 0x30);
dev->config.clock_out = pdata->clock_out;
u8 clock_out;
u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */
u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */
c->clock_out,
u8 clock_out;
.clock_out = 0,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = true,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = 0,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.clock_out = 3,
.clock_out = 0,