drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

305

static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

526

struct clk_state_registers_and_bypass s = { 0 };

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

237

static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

329

static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

395

static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

247

static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

255

static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

872

static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

619

static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

333

static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

435

struct clk_state_registers_and_bypass clk_register_dump;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

298

void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

355

struct clk_state_registers_and_bypass boot_snapshot;