drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1051

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1053

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1055

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1060

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1063

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1065

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

333

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

334

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

335

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

336

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1395

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1398

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

366

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

367

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

368

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

369

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1264

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1269

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1274

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1279

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1284

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1289

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1294

CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

371

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

372

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

373

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

374

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

375

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

376

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

377

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1104

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1108

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1112

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1116

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1120

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1124

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1130

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

409

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

410

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

411

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

412

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

413

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

414

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

415

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1148

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1150

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1152

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1157

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1160

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1162

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1347

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1349

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1354

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1357

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1359

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

359

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

360

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

361

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

362

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

952

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

954

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

959

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

962

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

964

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1161

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1163

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1165

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1170

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1173

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1175

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1363

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1365

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1370

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1373

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

359

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

360

clk_src_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

361

clk_src_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

362

clk_src_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

961

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

963

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

965

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

970

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

973

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

975

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1445

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1449

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1453

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1459

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1471

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

502

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

503

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

504

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

505

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

506

clk_src_regs(3, D)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

194

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

195

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

196

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

197

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

198

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

199

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

200

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2527

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2531

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2535

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2539

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2543

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2547

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2553

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1202

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1206

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1214

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

311

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

312

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

313

clk_src_regs(1, B)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1503

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1507

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1511

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1515

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1519

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1527

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

153

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

154

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

155

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

156

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

157

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

158

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

201

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

202

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

203

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

204

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

205

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

206

clk_src_regs(4, E),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

207

clk_src_regs(5, F)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2427

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2431

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2435

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2439

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2443

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2447

&clk_src_regs[5], false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2455

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1551

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1555

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1559

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1563

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1571

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

204

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

205

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

206

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

207

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

208

clk_src_regs(3, D)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1346

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1350

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1354

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1358

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1362

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1370

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

457

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

458

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

459

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

460

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

461

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

462

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1290

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1294

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1302

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

444

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

445

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

446

clk_src_regs(1, B)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2029

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2033

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2048

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2052

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2058

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2066

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

212

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

213

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

214

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

215

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

216

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

217

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

221

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

222

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

223

clk_src_regs(2, F),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

224

clk_src_regs(3, G),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

225

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1968

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1972

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1976

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1980

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1984

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1992

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

229

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

230

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

231

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

232

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

233

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

234

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1991

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1995

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1999

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2003

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2007

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2015

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

223

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

224

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

225

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

226

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

227

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

228

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1866

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1870

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1874

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1878

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1882

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1890

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

209

static const struct dce110_clk_src_regs clk_src_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

210

clk_src_regs(0, A),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

211

clk_src_regs(1, B),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

212

clk_src_regs(2, C),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

213

clk_src_regs(3, D),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

214

clk_src_regs(4, E)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

213

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2182

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2352

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2356

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2360

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2364

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2368

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2376

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1685

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1851

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1855

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1859

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1863

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1867

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1875

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

212

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1857

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2002

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2006

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2010

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2014

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2018

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2026

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

225

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1830

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1974

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1978

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1982

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1986

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1990

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1998

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

205

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1836

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1981

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1985

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1989

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1993

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1997

&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2005

&clk_src_regs[0], true);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

210

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1871

#define REG_STRUCT clk_src_regs

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

197

static struct dce110_clk_src_regs clk_src_regs[5];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2052

&clk_src_regs[0], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2056

&clk_src_regs[1], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2060

&clk_src_regs[2], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2064

&clk_src_regs[3], false);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2076

&clk_src_regs[0], true);