clk_set_min_rate
EXPORT_SYMBOL_GPL(clk_set_min_rate);
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate));
WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate));
ret = clk_set_min_rate(unicam->vpu_clock, UNICAM_MIN_VPU_CLOCK_RATE);
if (clk_set_min_rate(unicam->vpu_clock, 0))
if (clk_set_min_rate(unicam->vpu_clock, 0))
err = clk_set_min_rate(emc->clk, rate);
err = clk_set_min_rate(emc->clk, rate);
clk_set_min_rate(spisg->pclk, SPISG_PCLK_RATE_MIN);
int clk_set_min_rate(struct clk *clk, unsigned long rate);
DEFINE_EVENT(clk_rate, clk_set_min_rate,
clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1);
ret = clk_set_min_rate(dev->gclk, params_rate(params) *