clk_register_divider
return clk_register_divider(NULL, name, parent_name, clkflags,
return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
clk = clk_register_divider(NULL, clks[i].name,
clk = clk_register_divider(NULL, div[i].name, div[i].parent,
clk = clk_register_divider(NULL, np->name, parent_name, 0,
clk = clk_register_divider(NULL, list->name,
clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
prediv_clk = clk_register_divider(NULL, "pll2-prediv",
clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
clk = clk_register_divider(NULL, "sclk", "sclk_mux",
clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
clk_register_divider(NULL, "dev1_osc_div", "clk_m",
clk_register_divider(NULL, "dev2_osc_div", "clk_m",
clock = clk_register_divider(d->dev, child_name, parent_name, 0,
clk_register_divider(NULL, div0_name, mux_name,
clk_register_divider(NULL, div1_name, div0_name,
clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
clk_register_divider(NULL, "dci_div1", "dci_div0",
clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
clk_register_divider(NULL, "gem0_div1", "gem0_div0",
clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
clk_register_divider(NULL, "gem1_div1", "gem1_div0",
clk_register_divider(NULL, "can_div0", "can_mux", 0,
clk_register_divider(NULL, "can_div1", "can_div0",
clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,